[llvm] r205893 - [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:44:36 2014
New Revision: 205893

URL: http://llvm.org/viewvc/llvm-project?rev=205893&view=rev
Log:
[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

Modified:
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM64/memory.txt

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205893&r1=205892&r2=205893&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed Apr  9 09:44:36 2014
@@ -1368,10 +1368,10 @@ static DecodeStatus DecodeRegOffsetLdStI
 
   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
 
-  if (extendHi == 0x3)
+  if ((extendHi & 0x3) == 0x3)
     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
   else
-    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
 
   Inst.addOperand(MCOperand::CreateImm(extend));
   return Success;

Modified: llvm/trunk/test/MC/Disassembler/ARM64/memory.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/memory.txt?rev=205893&r1=205892&r2=205893&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/memory.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/memory.txt Wed Apr  9 09:44:36 2014
@@ -83,6 +83,8 @@
   0x64 0x00 0x00 0x39
   0x85 0x50 0x00 0x39
   0xe2 0x43 0x00 0x79
+  0x00 0xe8 0x20 0x38
+  0x00 0x48 0x20 0x38
 
 # CHECK: str	x4, [x3]
 # CHECK: str	x2, [sp, #32]
@@ -95,6 +97,8 @@
 # CHECK: strb	w4, [x3]
 # CHECK: strb	w5, [x4, #20]
 # CHECK: strh	w2, [sp, #32]
+# CHECK: strb	w0, [x0, x0, sxtx]
+# CHECK: strb	w0, [x0, w0, uxtw]
 
 #-----------------------------------------------------------------------------
 # Unscaled immediate loads and stores
@@ -422,11 +426,11 @@
   0xe1 0x6b 0xa3 0x3c
   0xe1 0x5b 0xa3 0x3c
 
-# CHECK: str	h0, [x0, x0, uxtw]
+# CHECK: str	h0, [x0, w0, uxtw]
 # CHECK: str	d1, [sp, x3]
-# CHECK: str	d1, [sp, x3, uxtw #3]
+# CHECK: str	d1, [sp, w3, uxtw #3]
 # CHECK: str	q1, [sp, x3]
-# CHECK: str	q1, [sp, x3, uxtw #4]
+# CHECK: str	q1, [sp, w3, uxtw #4]
 
 #-----------------------------------------------------------------------------
 # Load/Store exclusive