[llvm] r205891 - [ARM64] Add missing shifted register MVN alias to ORN

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:44:26 2014
New Revision: 205891

URL: http://llvm.org/viewvc/llvm-project?rev=205891&view=rev
Log:
[ARM64] Add missing shifted register MVN alias to ORN

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
    llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
    llvm/trunk/test/MC/ARM64/aliases.s

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td?rev=205891&r1=205890&r2=205891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td Wed Apr  9 09:44:26 2014
@@ -624,6 +624,11 @@ def : InstAlias<"mvn $Wd, $Wm",
 def : InstAlias<"mvn $Xd, $Xm",
                 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
 
+def : InstAlias<"mvn $Wd, $Wm, $sh",
+                (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
+def : InstAlias<"mvn $Xd, $Xm, $sh",
+                (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
+
 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
 

Modified: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp?rev=205891&r1=205890&r2=205891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp Wed Apr  9 09:44:26 2014
@@ -191,6 +191,14 @@ void ARM64InstPrinter::printInst(const M
     return;
   }
 
+  // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
+  // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
+  if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
+      (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
+    O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
+    printShiftedRegister(MI, 2, O);
+    return;
+  }
   // SUBS WZR, Wn, #imm ==> CMP Wn, #imm
   // SUBS XZR, Xn, #imm ==> CMP Xn, #imm
   if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||

Modified: llvm/trunk/test/MC/ARM64/aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/aliases.s?rev=205891&r1=205890&r2=205891&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/aliases.s (original)
+++ llvm/trunk/test/MC/ARM64/aliases.s Wed Apr  9 09:44:26 2014
@@ -159,6 +159,14 @@ foo:
 ; CHECK: mvn	x2, x3             ; encoding: [0xe2,0x03,0x23,0xaa]
 ; CHECK: mvn	w4, w9             ; encoding: [0xe4,0x03,0x29,0x2a]
 
+        mvn w4, w9, lsl #1
+        mvn x2, x3, lsl #1
+        orn w4, wzr, w9, lsl #1
+
+; CHECK: mvn	w4, w9, lsl #1     ; encoding: [0xe4,0x07,0x29,0x2a]
+; CHECK: mvn	x2, x3, lsl #1     ; encoding: [0xe2,0x07,0x23,0xaa]
+; CHECK: mvn	w4, w9, lsl #1     ; encoding: [0xe4,0x07,0x29,0x2a]
+
 ;-----------------------------------------------------------------------------
 ; Bitfield aliases
 ;-----------------------------------------------------------------------------