[llvm] r205884 - [ARM64] Rename FP to the UAL-compliant 'X29'.
Bradley Smith
bradley.smith at arm.com
Wed Apr 9 07:43:51 PDT 2014
Author: brasmi01
Date: Wed Apr 9 09:43:50 2014
New Revision: 205884
URL: http://llvm.org/viewvc/llvm-project?rev=205884&view=rev
Log:
[ARM64] Rename FP to the UAL-compliant 'X29'.
Modified:
llvm/trunk/lib/Target/ARM64/ARM64RegisterInfo.td
llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
llvm/trunk/test/CodeGen/ARM64/abi.ll
llvm/trunk/test/CodeGen/ARM64/abi_align.ll
llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll
llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll
llvm/trunk/test/CodeGen/ARM64/frameaddr.ll
llvm/trunk/test/CodeGen/ARM64/hello.ll
llvm/trunk/test/CodeGen/ARM64/patchpoint.ll
llvm/trunk/test/CodeGen/ARM64/returnaddr.ll
llvm/trunk/test/MC/ARM64/elf-relocs.s
llvm/trunk/test/MC/ARM64/memory.s
llvm/trunk/test/MC/ARM64/simd-ldst.s
llvm/trunk/test/MC/ARM64/tls-relocs.s
llvm/trunk/test/MC/Disassembler/ARM64/memory.txt
Modified: llvm/trunk/lib/Target/ARM64/ARM64RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64RegisterInfo.td?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64RegisterInfo.td Wed Apr 9 09:43:50 2014
@@ -112,7 +112,7 @@ def X25 : ARM64Reg<25, "x25", [W25]>,
def X26 : ARM64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
-def FP : ARM64Reg<29, "fp", [W29]>, DwarfRegAlias<W29>;
+def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
def LR : ARM64Reg<30, "lr", [W30]>, DwarfRegAlias<W30>;
def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Wed Apr 9 09:43:50 2014
@@ -1871,7 +1871,7 @@ int ARM64AsmParser::tryParseRegister() {
// Also handle a few aliases of registers.
if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase)
- .Case("x29", ARM64::FP)
+ .Case("fp", ARM64::FP)
.Case("x30", ARM64::LR)
.Case("x31", ARM64::XZR)
.Case("w31", ARM64::WZR)
Modified: llvm/trunk/test/CodeGen/ARM64/abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/abi.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/abi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/abi.ll Wed Apr 9 09:43:50 2014
@@ -77,6 +77,7 @@ entry:
; CHECK: fixed_4i
; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
; FAST: fixed_4i
+; FAST: sub sp, sp, #64
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
%0 = load <4 x i32>* %in, align 16
@@ -130,6 +131,7 @@ entry:
; CHECK: test3
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
; FAST: test3
+; FAST: sub sp, sp, #32
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
%0 = load <2 x i32>* %in, align 8
Modified: llvm/trunk/test/CodeGen/ARM64/abi_align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/abi_align.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/abi_align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/abi_align.ll Wed Apr 9 09:43:50 2014
@@ -294,7 +294,7 @@ entry:
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-24 = sp+72
; Space for s2 is allocated at sp+48
-; FAST: sub x[[A:[0-9]+]], fp, #24
+; FAST: sub x[[A:[0-9]+]], x29, #24
; FAST: add x[[A:[0-9]+]], sp, #48
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
@@ -317,17 +317,17 @@ declare i32 @f42_stack(i32 %i, i32 %i2,
define i32 @caller42_stack() #3 {
entry:
; CHECK: caller42_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
-; CHECK: stur {{x[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{x[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
; CHECK: str {{x[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
; Space for s2 is allocated at sp+32
; CHECK: add x[[B:[0-9]+]], sp, #32
; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
@@ -336,8 +336,8 @@ entry:
; FAST: caller42_stack
; Space for s1 is allocated at fp-24
; Space for s2 is allocated at fp-48
-; FAST: sub x[[A:[0-9]+]], fp, #24
-; FAST: sub x[[B:[0-9]+]], fp, #48
+; FAST: sub x[[A:[0-9]+]], x29, #24
+; FAST: sub x[[B:[0-9]+]], x29, #48
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
; FAST: str {{w[0-9]+}}, [sp]
@@ -399,7 +399,7 @@ entry:
; Space for s2 is allocated at sp
; FAST: caller43
-; FAST: mov fp, sp
+; FAST: mov x29, sp
; Space for s1 is allocated at sp+32
; Space for s2 is allocated at sp
; FAST: add x1, sp, #32
@@ -429,17 +429,17 @@ declare i32 @f43_stack(i32 %i, i32 %i2,
define i32 @caller43_stack() #3 {
entry:
; CHECK: caller43_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
-; CHECK: stur {{q[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{q[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
; CHECK: str {{q[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
; Space for s2 is allocated at sp+32
; CHECK: add x[[B:[0-9]+]], sp, #32
; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
; Address of s1 is passed on stack at sp+8
; CHECK: str x[[A]], [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #9
@@ -449,12 +449,12 @@ entry:
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-32 = sp+64
; Space for s2 is allocated at sp+32
-; FAST: sub x[[A:[0-9]+]], fp, #32
+; FAST: sub x[[A:[0-9]+]], x29, #32
; FAST: add x[[B:[0-9]+]], sp, #32
-; FAST: stur {{x[0-9]+}}, [fp, #-32]
-; FAST: stur {{x[0-9]+}}, [fp, #-24]
-; FAST: stur {{x[0-9]+}}, [fp, #-16]
-; FAST: stur {{x[0-9]+}}, [fp, #-8]
+; FAST: stur {{x[0-9]+}}, [x29, #-32]
+; FAST: stur {{x[0-9]+}}, [x29, #-24]
+; FAST: stur {{x[0-9]+}}, [x29, #-16]
+; FAST: stur {{x[0-9]+}}, [x29, #-8]
; FAST: str {{x[0-9]+}}, [sp, #32]
; FAST: str {{x[0-9]+}}, [sp, #40]
; FAST: str {{x[0-9]+}}, [sp, #48]
@@ -487,6 +487,7 @@ entry:
; CHECK: str {{w[0-9]+}}, [sp, #16]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
; FAST: i128_split
+; FAST: sub sp, sp, #48
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str {{w[0-9]+}}, [x[[ADDR]], #16]
; FAST: stp {{x[0-9]+}}, {{x[0-9]+}}, [x[[ADDR]]]
Modified: llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll Wed Apr 9 09:43:50 2014
@@ -14,6 +14,7 @@ entry:
define void @main() nounwind {
entry:
; CHECK: main
+; CHECK: mov x29, sp
; CHECK: mov x[[REG:[0-9]+]], sp
; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
Modified: llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll Wed Apr 9 09:43:50 2014
@@ -24,8 +24,8 @@ entry:
define i32 @foo1(i32 %a) nounwind {
entry:
; CHECK: foo1
-; CHECK: stur w0, [fp, #-4]
-; CHECK-NEXT: ldur w0, [fp, #-4]
+; CHECK: stur w0, [x29, #-4]
+; CHECK-NEXT: ldur w0, [x29, #-4]
; CHECK-NEXT: bl _call1
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
Modified: llvm/trunk/test/CodeGen/ARM64/frameaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/frameaddr.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/frameaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/frameaddr.ll Wed Apr 9 09:43:50 2014
@@ -3,10 +3,10 @@
define i8* @t() nounwind {
entry:
; CHECK-LABEL: t:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: mov x0, fp
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: stp x29, lr, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: mov x0, x29
+; CHECK: ldp x29, lr, [sp], #16
; CHECK: ret
%0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0
Modified: llvm/trunk/test/CodeGen/ARM64/hello.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/hello.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/hello.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/hello.ll Wed Apr 9 09:43:50 2014
@@ -2,27 +2,27 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
; CHECK-LABEL: main:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK-NEXT: mov fp, sp
+; CHECK: stp x29, lr, [sp, #-16]!
+; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: stur wzr, [fp, #-4]
+; CHECK-NEXT: stur wzr, [x29, #-4]
; CHECK: adrp x0, L_.str at PAGE
; CHECK: add x0, x0, L_.str at PAGEOFF
; CHECK-NEXT: bl _puts
-; CHECK-NEXT: mov sp, fp
-; CHECK-NEXT: ldp fp, lr, [sp], #16
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, lr, [sp], #16
; CHECK-NEXT: ret
; CHECK-LINUX-LABEL: main:
-; CHECK-LINUX: stp fp, lr, [sp, #-16]!
-; CHECK-LINUX-NEXT: mov fp, sp
+; CHECK-LINUX: stp x29, lr, [sp, #-16]!
+; CHECK-LINUX-NEXT: mov x29, sp
; CHECK-LINUX-NEXT: sub sp, sp, #16
-; CHECK-LINUX-NEXT: stur wzr, [fp, #-4]
+; CHECK-LINUX-NEXT: stur wzr, [x29, #-4]
; CHECK-LINUX: adrp x0, .L.str
; CHECK-LINUX: add x0, x0, :lo12:.L.str
; CHECK-LINUX-NEXT: bl puts
-; CHECK-LINUX-NEXT: mov sp, fp
-; CHECK-LINUX-NEXT: ldp fp, lr, [sp], #16
+; CHECK-LINUX-NEXT: mov sp, x29
+; CHECK-LINUX-NEXT: ldp x29, lr, [sp], #16
; CHECK-LINUX-NEXT: ret
@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00"
Modified: llvm/trunk/test/CodeGen/ARM64/patchpoint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/patchpoint.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/patchpoint.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/patchpoint.ll Wed Apr 9 09:43:50 2014
@@ -25,10 +25,10 @@ entry:
; as a leaf function.
;
; CHECK-LABEL: caller_meta_leaf
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
; CHECK-NEXT: sub sp, sp, #32
; CHECK: Ltmp
-; CHECK: mov sp, fp
+; CHECK: mov sp, x29
; CHECK: ret
define void @caller_meta_leaf() {
Modified: llvm/trunk/test/CodeGen/ARM64/returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/returnaddr.ll?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/returnaddr.ll Wed Apr 9 09:43:50 2014
@@ -12,12 +12,12 @@ entry:
define i8* @rt2() nounwind readnone {
entry:
; CHECK-LABEL: rt2:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: ldr x[[REG:[0-9]+]], [fp]
+; CHECK: stp x29, lr, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: ldr x[[REG:[0-9]+]], [x29]
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
; CHECK: ldr x0, [x[[REG2]], #8]
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: ldp x29, lr, [sp], #16
; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 2)
ret i8* %0
Modified: llvm/trunk/test/MC/ARM64/elf-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/elf-relocs.s?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/elf-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/elf-relocs.s Wed Apr 9 09:43:50 2014
@@ -72,7 +72,7 @@
// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
-// CHECK: adrp fp, :gottprel:sym
+// CHECK: adrp x29, :gottprel:sym
// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
@@ -105,7 +105,7 @@ trickQuestion:
ldrsb w23, [x19, #:dtprel_lo12:sym]
ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
ldr b11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
@@ -144,7 +144,7 @@ trickQuestion:
ldrsh w23, [x19, #:dtprel_lo12:sym]
ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
ldr h11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
Modified: llvm/trunk/test/MC/ARM64/memory.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/memory.s?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/memory.s (original)
+++ llvm/trunk/test/MC/ARM64/memory.s Wed Apr 9 09:43:50 2014
@@ -208,7 +208,7 @@ foo:
; Pre-indexed loads and stores
;-----------------------------------------------------------------------------
- ldr fp, [x7, #8]!
+ ldr x29, [x7, #8]!
ldr lr, [x7, #8]!
ldr b5, [x0, #1]!
ldr h6, [x0, #2]!
@@ -217,14 +217,14 @@ foo:
ldr q9, [x0, #16]!
str lr, [x7, #-8]!
- str fp, [x7, #-8]!
+ str x29, [x7, #-8]!
str b5, [x0, #-1]!
str h6, [x0, #-2]!
str s7, [x0, #-4]!
str d8, [x0, #-8]!
str q9, [x0, #-16]!
-; CHECK: ldr fp, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
+; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
@@ -233,7 +233,7 @@ foo:
; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
-; CHECK: str fp, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
+; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
@@ -244,14 +244,14 @@ foo:
; post-indexed loads and stores
;-----------------------------------------------------------------------------
str lr, [x7], #-8
- str fp, [x7], #-8
+ str x29, [x7], #-8
str b5, [x0], #-1
str h6, [x0], #-2
str s7, [x0], #-4
str d8, [x0], #-8
str q9, [x0], #-16
- ldr fp, [x7], #8
+ ldr x29, [x7], #8
ldr lr, [x7], #8
ldr b5, [x0], #1
ldr h6, [x0], #2
@@ -260,14 +260,14 @@ foo:
ldr q9, [x0], #16
; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
-; CHECK: str fp, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
+; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
-; CHECK: ldr fp, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
+; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
@@ -545,8 +545,8 @@ foo:
; unambiguous, i.e. negative or unaligned."
;-----------------------------------------------------------------------------
- ldr x11, [fp, #-8]
- ldr x11, [fp, #7]
+ ldr x11, [x29, #-8]
+ ldr x11, [x29, #7]
ldr w0, [x0, #2]
ldr w0, [x0, #-256]
ldr b2, [x1, #-2]
@@ -559,8 +559,8 @@ foo:
ldr q5, [x8, #8]
ldr q5, [x9, #-16]
-; CHECK: ldur x11, [fp, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
-; CHECK: ldur x11, [fp, #7] ; encoding: [0xab,0x73,0x40,0xf8]
+; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
+; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8]
; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
@@ -573,8 +573,8 @@ foo:
; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
- str x11, [fp, #-8]
- str x11, [fp, #7]
+ str x11, [x29, #-8]
+ str x11, [x29, #7]
str w0, [x0, #2]
str w0, [x0, #-256]
str b2, [x1, #-2]
@@ -587,8 +587,8 @@ foo:
str q5, [x8, #8]
str q5, [x9, #-16]
-; CHECK: stur x11, [fp, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
-; CHECK: stur x11, [fp, #7] ; encoding: [0xab,0x73,0x00,0xf8]
+; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
+; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8]
; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
Modified: llvm/trunk/test/MC/ARM64/simd-ldst.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/simd-ldst.s?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/simd-ldst.s (original)
+++ llvm/trunk/test/MC/ARM64/simd-ldst.s Wed Apr 9 09:43:50 2014
@@ -263,10 +263,10 @@ ld3st3_multiple:
; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x40,0x0c]
+; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c]
; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c]
; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v4, v5, v6 }, [fp] ; encoding: [0xa4,0x4b,0x40,0x4c]
+; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c]
; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c]
@@ -279,10 +279,10 @@ ld3st3_multiple:
; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c]
; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c]
-; CHECK: st3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x00,0x0c]
+; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c]
; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c]
; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v7, v8, v9 }, [fp] ; encoding: [0xa7,0x4b,0x00,0x4c]
+; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c]
ld4st4_multiple:
Modified: llvm/trunk/test/MC/ARM64/tls-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/tls-relocs.s?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/tls-relocs.s Wed Apr 9 09:43:50 2014
@@ -121,7 +121,7 @@
ldrsb x29, [x28, #:tprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
@@ -245,7 +245,7 @@
ldrsb x29, [x28, #:dtprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
Modified: llvm/trunk/test/MC/Disassembler/ARM64/memory.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/memory.txt?rev=205884&r1=205883&r2=205884&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/memory.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/memory.txt Wed Apr 9 09:43:50 2014
@@ -210,7 +210,7 @@
0x08 0x8c 0x40 0xfc
0x09 0x0c 0xc1 0x3c
-# CHECK: ldr fp, [x7, #8]!
+# CHECK: ldr x29, [x7, #8]!
# CHECK: ldr lr, [x7, #8]!
# CHECK: ldr b5, [x0, #1]!
# CHECK: ldr h6, [x0, #2]!
@@ -227,7 +227,7 @@
0x09 0x0c 0x9f 0x3c
# CHECK: str lr, [x7, #-8]!
-# CHECK: str fp, [x7, #-8]!
+# CHECK: str x29, [x7, #-8]!
# CHECK: str b5, [x0, #-1]!
# CHECK: str h6, [x0, #-2]!
# CHECK: str s7, [x0, #-4]!
@@ -247,7 +247,7 @@
0x09 0x04 0x9f 0x3c
# CHECK: str lr, [x7], #-8
-# CHECK: str fp, [x7], #-8
+# CHECK: str x29, [x7], #-8
# CHECK: str b5, [x0], #-1
# CHECK: str h6, [x0], #-2
# CHECK: str s7, [x0], #-4
@@ -262,7 +262,7 @@
0x08 0x84 0x40 0xfc
0x09 0x04 0xc1 0x3c
-# CHECK: ldr fp, [x7], #8
+# CHECK: ldr x29, [x7], #8
# CHECK: ldr lr, [x7], #8
# CHECK: ldr b5, [x0], #1
# CHECK: ldr h6, [x0], #2
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