[llvm] r205877 - [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:43:15 2014
New Revision: 205877

URL: http://llvm.org/viewvc/llvm-project?rev=205877&view=rev
Log:
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
    llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
    llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td?rev=205877&r1=205876&r2=205877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td Wed Apr  9 09:43:15 2014
@@ -1200,9 +1200,13 @@ class MulHi<bits<3> opc, string asm, SDN
   let Inst{31-24} = 0b10011011;
   let Inst{23-21} = opc;
   let Inst{20-16} = Rm;
-  let Inst{15-10} = 0b011111;
+  let Inst{15}    = 0;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
+
+  // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
+  // (i.e. all bits 1) but is ignored by the processor.
+  let PostEncoderMethod = "fixMulHigh";
 }
 
 class MulAccumWAlias<string asm, Instruction inst>

Modified: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp?rev=205877&r1=205876&r2=205877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp Wed Apr  9 09:43:15 2014
@@ -177,6 +177,9 @@ public:
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const;
 
+  unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
+                      const MCSubtargetInfo &STI) const;
+
   template<int hasRs, int hasRt2> unsigned
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
                         const MCSubtargetInfo &STI) const;
@@ -565,6 +568,16 @@ void ARM64MCCodeEmitter::EncodeInstructi
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 }
 
+unsigned
+ARM64MCCodeEmitter::fixMulHigh(const MCInst &MI,
+                               unsigned EncodedValue,
+                               const MCSubtargetInfo &STI) const {
+  // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
+  // (i.e. all bits 1) but is ignored by the processor.
+  EncodedValue |= 0x1f << 10;
+  return EncodedValue;
+}
+
 template<int hasRs, int hasRt2> unsigned
 ARM64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
                                           unsigned EncodedValue,

Modified: llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt?rev=205877&r1=205876&r2=205877&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt Wed Apr  9 09:43:15 2014
@@ -3,3 +3,7 @@
 0x00 0x08 0x00 0xc8
 
 # CHECK: stxr	w0, x0, [x0]
+
+0x00 0x00 0x40 0x9b
+
+# CHECK: smulh x0, x0, x0