[llvm] r205859 - [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

[Bradley Smith]

Author: brasmi01
Date: Wed Apr  9 09:41:45 2014
New Revision: 205859

URL: http://llvm.org/viewvc/llvm-project?rev=205859&view=rev
Log:
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

Modified:
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205859&r1=205858&r2=205859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed Apr  9 09:41:45 2014
@@ -906,6 +906,8 @@ static DecodeStatus DecodeMoveImmInstruc
   case ARM64::MOVZWi:
   case ARM64::MOVNWi:
   case ARM64::MOVKWi:
+    if (shift & (1U << 5))
+      return Fail;
     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
     break;
   case ARM64::MOVZXi:
@@ -1339,6 +1341,10 @@ static DecodeStatus DecodeAddSubERegInst
   unsigned Rm = fieldFromInstruction(insn, 16, 5);
   unsigned extend = fieldFromInstruction(insn, 10, 6);
 
+  unsigned shift = extend & 0x7;
+  if (shift > 4)
+    return Fail;
+
   switch (Inst.getOpcode()) {
   default:
     return Fail;

Modified: llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt?rev=205859&r1=205858&r2=205859&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt Wed Apr  9 09:41:45 2014
@@ -2,6 +2,15 @@
 
 # LDR/STR: undefined if option field is 10x or 00x.
 # RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x88 0x00 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
+
+# Instructions notionally in the add/sub (extended register) sheet, but with
+# invalid shift amount or "opt" field.
+# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
+
+# MOVK with sf == 0 and hw<1> == 1 is unallocated.
+# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
 
 # CHECK: invalid instruction encoding