[llvm] r205622 - Fix for PR18921 (LDRD/STRD part)::
Stepan Dyatkovskiy
stpworld at narod.ru
Fri Apr 4 03:17:56 PDT 2014
Author: dyatkovskiy
Date: Fri Apr 4 05:17:56 2014
New Revision: 205622
URL: http://llvm.org/viewvc/llvm-project?rev=205622&view=rev
Log:
Fix for PR18921 (LDRD/STRD part)::
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.
Added:
llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s
llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm.s
llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s
llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb.s
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=205622&r1=205621&r2=205622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Apr 4 05:17:56 2014
@@ -2282,12 +2282,6 @@ let mayLoad = 1, neverHasSideEffects = 1
def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
Requires<[IsARM, HasV5TE]>;
-
- // GNU Assembler extension (compatibility)
- let isAsmParserOnly = 1 in
- def LDRD_PAIR : AI3ld<0b1101, 0, (outs GPRPairOp:$Rt), (ins addrmode3:$addr),
- LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $addr", []>,
- Requires<[IsARM, HasV5TE]>;
}
def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
@@ -2557,14 +2551,6 @@ let mayStore = 1, neverHasSideEffects =
Requires<[IsARM, HasV5TE]> {
let Inst{21} = 0;
}
-
- // GNU Assembler extension (compatibility)
- let isAsmParserOnly = 1 in
- def STRD_PAIR : AI3str<0b1111, (outs), (ins GPRPairOp:$Rt, addrmode3:$addr),
- StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $addr", []>,
- Requires<[IsARM, HasV5TE]> {
- let Inst{21} = 0;
- }
}
// Indexed stores
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=205622&r1=205621&r2=205622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Apr 4 05:17:56 2014
@@ -5404,21 +5404,24 @@ bool ARMAsmParser::ParseInstruction(Pars
}
// GNU Assembler extension (compatibility)
- if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
- Operands.size() == 4) {
- ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
- assert(Op->isReg() && "expected register argument");
-
- unsigned SuperReg = MRI->getMatchingSuperReg(
- Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
-
- assert(SuperReg && "expected register pair");
-
- unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
-
- Operands.insert(Operands.begin() + 3,
- ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
- Op->getEndLoc()));
+ if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
+ ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
+ ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
+ if (Op3->isMem()) {
+ assert(Op2->isReg() && "expected register argument");
+
+ unsigned SuperReg = MRI->getMatchingSuperReg(
+ Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
+
+ assert(SuperReg && "expected register pair");
+
+ unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
+
+ Operands.insert(Operands.begin() + 3,
+ ARMOperand::CreateReg(PairedReg,
+ Op2->getStartLoc(),
+ Op2->getEndLoc()));
+ }
}
// FIXME: As said above, this is all a pretty gross hack. This instruction
Added: llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s?rev=205622&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s (added)
+++ llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s Fri Apr 4 05:17:56 2014
@@ -0,0 +1,9 @@
+@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
+.text
+@ CHECK: error: instruction requires: thumb2
+@ CHECK: ldrd r0, [r0, #512]
+ ldrd r0, [r0, #512]
+
+@ CHECK: error: instruction requires: thumb2
+@ CHECK: strd r0, [r0, #512]
+ strd r0, [r0, #512]
Added: llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm.s?rev=205622&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm.s (added)
+++ llvm/trunk/test/MC/ARM/ldrd-strd-gnu-arm.s Fri Apr 4 05:17:56 2014
@@ -0,0 +1,20 @@
+@ PR18921
+@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
+.text
+
+@ CHECK-NOT: .code 16
+
+
+@ CHECK: ldrd r0, r1, [r10, #32]! @ encoding: [0xd0,0x02,0xea,0xe1]
+@ CHECK: ldrd r0, r1, [r10], #32 @ encoding: [0xd0,0x02,0xca,0xe0]
+@ CHECK: ldrd r0, r1, [r10, #32] @ encoding: [0xd0,0x02,0xca,0xe1]
+ ldrd r0, [r10, #32]!
+ ldrd r0, [r10], #32
+ ldrd r0, [r10, #32]
+
+@ CHECK: strd r0, r1, [r10, #32]! @ encoding: [0xf0,0x02,0xea,0xe1]
+@ CHECK: strd r0, r1, [r10], #32 @ encoding: [0xf0,0x02,0xca,0xe0]
+@ CHECK: strd r0, r1, [r10, #32] @ encoding: [0xf0,0x02,0xca,0xe1]
+ strd r0, [r10, #32]!
+ strd r0, [r10], #32
+ strd r0, [r10, #32]
Added: llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s?rev=205622&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s (added)
+++ llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s Fri Apr 4 05:17:56 2014
@@ -0,0 +1,10 @@
+@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
+.text
+.thumb
+@ CHECK: error: invalid operand for instruction
+@ CHECK: ldrd r12, [r0, #512]
+ ldrd r12, [r0, #512]
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: strd r12, [r0, #512]
+ strd r12, [r0, #512]
Added: llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb.s?rev=205622&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb.s (added)
+++ llvm/trunk/test/MC/ARM/ldrd-strd-gnu-thumb.s Fri Apr 4 05:17:56 2014
@@ -0,0 +1,20 @@
+@ PR18921
+@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
+.text
+.thumb
+
+@ CHECK: .code 16
+
+@ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
+@ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
+@ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
+ ldrd r0, [r10, #512]!
+ ldrd r0, [r10], #512
+ ldrd r0, [r10, #512]
+
+@ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01]
+@ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01]
+@ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01]
+ strd r0, [r10, #512]!
+ strd r0, [r10], #512
+ strd r0, [r10, #512]
More information about the llvm-commits
mailing list