[PATCH] Fixed STRD register classes for Thumb2 mode.

[Stepan Dyatkovskiy]

Hi t.p.northover, rengolin,

Test-case is based on thumb2-ldrd.

http://llvm-reviews.chandlerc.com/D3287

Files:
  lib/Target/ARM/ARMInstrThumb2.td
  test/MC/ARM/thumb2-strd.s

Index: lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- lib/Target/ARM/ARMInstrThumb2.td
+++ lib/Target/ARM/ARMInstrThumb2.td
@@ -1445,7 +1445,7 @@
 // Store doubleword
 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
-                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
+                       (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
                IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
 
 // Indexed stores
Index: test/MC/ARM/thumb2-strd.s
===================================================================
--- /dev/null
+++ test/MC/ARM/thumb2-strd.s
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple armv7-linux-gnueabi < %s >/dev/null 2> %t
+// RUN: grep "error: invalid operand for instruction" %t | count 3
+.text
+.thumb
+
+// That should pass, everything is OK for Thumb2 mode.
+strd r10, r11, [r0, #256]
+strd r10, r11, [r0, #256]!
+strd r10, r11, [r0], #256
+
+// That should trigger 3 error messages.
+// Since r12:SP pair is not allowed in T2.
+strd r12, SP, [r0, #256]
+strd r12, SP, [r0, #256]!
+strd r12, SP, [r0], #256
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