[PATCH][mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu
Kai Nacke
kai.nacke at redstar.de
Thu Apr 3 12:41:32 PDT 2014
Hi all!
Yet another Octeon-related patch:
This patch adds the Octeon cnMips instructions seqi/snei and
v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included.
Regards,
Kai
-------------- next part --------------
From 5719672ba55a0ffb82d51ce4dd3ed3a0c88cb240 Mon Sep 17 00:00:00 2001
From: kai <kai at redstar.de>
Date: Thu, 3 Apr 2014 09:20:14 +0200
Subject: [PATCH] [mips] Add Octeon cnMips instructions seqi/snei and
v3mulu/vmm0/vmulu.
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.
---
lib/Target/Mips/Mips64InstrInfo.td | 34 ++++++++++++++++++++++++++++++++++
lib/Target/Mips/MipsInstrFormats.td | 14 ++++++++++++++
test/MC/Mips/octeon-instructions.s | 20 ++++++++++++++++++++
3 files changed, 68 insertions(+)
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 7115d11..c560376 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -20,6 +20,9 @@ def uimm16_64 : Operand<i64> {
let PrintMethod = "printUnsignedImm";
}
+// Signed Operand
+def simm10_64 : Operand<i64>;
+
// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
return getImm(N, (unsigned)N->getZExtValue() - 32);
@@ -28,6 +31,11 @@ def Subtract32 : SDNodeXForm<imm, [{
// shamt must fit in 6 bits.
def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
+// Node immediate fits as 10-bit sign extended on target immediate.
+// e.g. seqi, snei
+def immSExt10_64 : PatLeaf<(i64 imm),
+ [{ return isInt<10>(N->getSExtValue()); }]>;
+
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
@@ -254,6 +262,14 @@ class SetCC64_R<string opstr, PatFrag cond_op> :
let TwoOperandAliasConstraint = "$rd = $rs";
}
+class SetCC64_I<string opstr, PatFrag cond_op>:
+ InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
+ !strconcat(opstr, "\t$rt, $rs, $imm10"),
+ [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
+ II_SEQI_SNEI, FrmI, opstr> {
+ let TwoOperandAliasConstraint = "$rt = $rs";
+}
+
// Unsigned Byte Add
let Pattern = [(set GPR64Opnd:$rd,
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
@@ -287,7 +303,25 @@ def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
// Set on equal/not equal
def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
+def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
+def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
+
+// 192-bit × 64-bit Unsigned Multiply and Add
+let Defs = [P0, P1, P2] in
+def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
+ ADD_FM<0x1c, 0x11>;
+
+// 64-bit Unsigned Multiply and Add Move
+let Defs = [MPL0, P0, P1, P2] in
+def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
+ ADD_FM<0x1c, 0x10>;
+
+// 64-bit Unsigned Multiply and Add
+let Defs = [MPL1, MPL2, P0, P1, P2] in
+def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
+ ADD_FM<0x1c, 0x0f>;
+
}
}
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index e4405ab..3655317 100644
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -545,6 +545,20 @@ class SEQ_FM<bits<6> funct> : StdArch {
let Inst{5-0} = funct;
}
+class SEQI_FM<bits<6> funct> : StdArch {
+ bits<5> rs;
+ bits<5> rt;
+ bits<10> imm10;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x1c;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = rt;
+ let Inst{15-6} = imm10;
+ let Inst{5-0} = funct;
+}
+
//===----------------------------------------------------------------------===//
// System calls format <op|code_|funct>
//===----------------------------------------------------------------------===//
diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s
index 0244e19..b7c89b4 100644
--- a/test/MC/Mips/octeon-instructions.s
+++ b/test/MC/Mips/octeon-instructions.s
@@ -29,8 +29,18 @@
# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c]
# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a]
+# CHECK: seqi $17, $15, -512 # encoding: [0x71,0xf1,0x80,0x2e]
+# CHECK: seqi $16, $16, 38 # encoding: [0x72,0x10,0x09,0xae]
# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b]
+# CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef]
+# CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef]
+# CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11]
+# CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11]
+# CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10]
+# CHECK: vmm0 $ra, $ra, $9 # encoding: [0x73,0xe9,0xf8,0x10]
+# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f]
+# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f]
baddu $9, $6, $7
baddu $17, $18, $19
@@ -61,5 +71,15 @@
pop $2
seq $25, $23, $24
seq $6, $24
+ seqi $17, $15, -512
+ seqi $16, 38
sne $25, $23, $24
sne $23, $20
+ snei $4, $16, -313
+ snei $26, 511
+ v3mulu $21, $10, $21
+ v3mulu $20, $10
+ vmm0 $3, $19, $16
+ vmm0 $31, $9
+ vmulu $29, $10, $17
+ vmulu $27, $6
--
1.8.0.msysgit.0
More information about the llvm-commits
mailing list