[PATCH] Add support for load folding of avx1 logical instructions

[Cameron McInally]

Ah, okay. That leads me to some other questions...

Did you intend to pick up the 'andn' pattern fragment from
X86InstrAVX512.td? If so, it seems like that definition should be
moved out of X86InstrAVX512.td to somewhere more general.

Or should the operator have been the X86 specific "X86andnp", like the
other ANDN patterns in X86InstrSSE.td?

Either way... how would you feel about moving this patch under the
definitions of the AVX FP logicals. A little awkward, but I think it's
a better fit than in X86InstrCompiler.td.

-Cameron

On Wed, Apr 2, 2014 at 5:33 PM, Louis Gerbarg <lgg at apple.com> wrote:
> The logic behind it was that where it looked like it made sense in X86InstrSSE.td around line 500 was before the definitions of the instructions I needed, and I didn’t want to try to re-order the file or make a new section in the file with these patterns, so after talking to Jim I decided to put them in X86 nstrCompiler so I would have all the definitions from X86InstrSSE.td.
>
> Louis
>
> On Apr 2, 2014, at 7:33 AM, Cameron McInally <cameron.mcinally at nyu.edu> wrote:
>
>> Just curious… why did this change go into X86InstrCompiler.td and not
>> X86InstrSSE.td?
>>
>> Tia,
>> Cameron
>>
>> On Wed, Apr 2, 2014 at 12:41 AM, Nadav Rotem <nrotem at apple.com> wrote:
>>> LGTM!
>>>
>>> On Apr 1, 2014, at 3:48 PM, Louis Gerbarg <lgg at apple.com> wrote:
>>>
>>>> <0001-Add-support-for-load-folding-of-avx1-logical-instruc.patch>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
-------------- next part --------------
Index: lib/Target/X86/X86InstrSSE.td
===================================================================
--- lib/Target/X86/X86InstrSSE.td	(revision 205478)
+++ lib/Target/X86/X86InstrSSE.td	(working copy)
@@ -2973,6 +2973,19 @@
 let isCommutable = 0 in
   defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
 
+// AVX1 requires type coercions in order to fold loads directly into logical
+// operations.
+let Predicates = [HasAVX1Only] in {
+    def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
+              (VANDPSYrm VR256:$src1, addr:$src2)>;
+    def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
+              (VORPSYrm VR256:$src1, addr:$src2)>;
+    def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
+              (VXORPSYrm VR256:$src1, addr:$src2)>;
+    def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
+              (VANDNPSYrm VR256:$src1, addr:$src2)>;
+}
+
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Arithmetic Instructions
 //===----------------------------------------------------------------------===//