[llvm] r205343 - [mips] Add Octeon cnMips instructions mtmX and mtpX

[Kai Nacke]

Author: redstar
Date: Tue Apr  1 13:35:26 2014
New Revision: 205343

URL: http://llvm.org/viewvc/llvm-project?rev=205343&view=rev
Log:
[mips] Add Octeon cnMips instructions mtmX and mtpX

Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders at imgtec.com

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/test/MC/Mips/octeon-instructions.s

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=205343&r1=205342&r2=205343&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Apr  1 13:35:26 2014
@@ -257,6 +257,14 @@ let Defs = [HI0, LO0, P0, P1, P2] in
 def DMUL  : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
                               ADD_FM<0x1c, 0x03>;
 
+// Move to multiplier/product register
+def MTM0   : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
+def MTM1   : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
+def MTM2   : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
+def MTP0   : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
+def MTP1   : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
+def MTP2   : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
+
 // Count Ones in a Word/Doubleword
 def POP   : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
 def DPOP  : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=205343&r1=205342&r2=205343&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Apr  1 13:35:26 2014
@@ -489,6 +489,17 @@ class WAIT_FM : StdArch {
   let Inst{5-0}   = 0x20;
 }
 
+class MTMR_FM<bits<6> funct> : StdArch {
+  bits<5> rs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x1c;
+  let Inst{25-21} = rs;
+  let Inst{20-6}  = 0;
+  let Inst{5-0}   = funct;
+}
+
 class POP_FM<bits<6> funct> : StdArch {
   bits<5> rd;
   bits<5> rs;

Modified: llvm/trunk/test/MC/Mips/octeon-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/octeon-instructions.s?rev=205343&r1=205342&r2=205343&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/octeon-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/octeon-instructions.s Tue Apr  1 13:35:26 2014
@@ -7,6 +7,12 @@
 # CHECK: dmul  $19, $24, $25          # encoding: [0x73,0x19,0x98,0x03]
 # CHECK: dpop  $9, $6                 # encoding: [0x70,0xc0,0x48,0x2d]
 # CHECK: dpop  $15, $22               # encoding: [0x72,0xc0,0x78,0x2d]
+# CHECK: mtm0  $15                    # encoding: [0x71,0xe0,0x00,0x08]
+# CHECK: mtm1  $16                    # encoding: [0x72,0x00,0x00,0x0c]
+# CHECK: mtm2  $17                    # encoding: [0x72,0x20,0x00,0x0d]
+# CHECK: mtp0  $18                    # encoding: [0x72,0x40,0x00,0x09]
+# CHECK: mtp1  $19                    # encoding: [0x72,0x60,0x00,0x0a]
+# CHECK: mtp2  $20                    # encoding: [0x72,0x80,0x00,0x0b]
 # CHECK: pop   $9, $6                 # encoding: [0x70,0xc0,0x48,0x2c]
 # CHECK: pop   $8, $19                # encoding: [0x72,0x60,0x40,0x2c]
 # CHECK: seq   $25, $23, $24          # encoding: [0x72,0xf8,0xc8,0x2a]
@@ -19,6 +25,12 @@
   dmul  $19, $24, $25
   dpop  $9, $6
   dpop  $15, $22
+  mtm0  $15
+  mtm1  $16
+  mtm2  $17
+  mtp0  $18
+  mtp1  $19
+  mtp2  $20
   pop   $9, $6
   pop   $8, $19
   seq   $25, $23, $24