[llvm] r205301 - Fixing warnings in the MSVC build. No functional changes intended.
Aaron Ballman
aaron at aaronballman.com
Tue Apr 1 05:22:23 PDT 2014
Author: aaronballman
Date: Tue Apr 1 07:22:20 2014
New Revision: 205301
URL: http://llvm.org/viewvc/llvm-project?rev=205301&view=rev
Log:
Fixing warnings in the MSVC build. No functional changes intended.
Modified:
llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp
llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
Modified: llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp?rev=205301&r1=205300&r2=205301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64FastISel.cpp Tue Apr 1 07:22:20 2014
@@ -1918,7 +1918,7 @@ bool ARM64FastISel::TargetSelectInstruct
}
return false;
// Silence warnings.
- (void)CC_ARM64_DarwinPCS_VarArg;
+ (void)&CC_ARM64_DarwinPCS_VarArg;
}
namespace llvm {
Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=205301&r1=205300&r2=205301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Tue Apr 1 07:22:20 2014
@@ -1740,9 +1740,9 @@ static SDValue LowerPREFETCH(SDValue Op,
}
// built the mask value encoding the expected behavior.
- unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
- (Locality << 1) | // Cache level bits
- IsStream; // Stream bit
+ unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
+ (Locality << 1) | // Cache level bits
+ (unsigned)IsStream; // Stream bit
return DAG.getNode(ARM64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
}
Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=205301&r1=205300&r2=205301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Tue Apr 1 07:22:20 2014
@@ -3021,17 +3021,17 @@ bool ARM64AsmParser::tryParseVectorRegis
const MCExpr *ImmVal;
if (getParser().parseExpression(ImmVal))
- return MatchOperand_ParseFail;
+ return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
if (!MCE) {
TokError("immediate value expected for vector index");
- return MatchOperand_ParseFail;
+ return false;
}
SMLoc E = getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac)) {
Error(E, "']' expected");
- return MatchOperand_ParseFail;
+ return false;
}
Parser.Lex(); // Eat right bracket token.
@@ -3401,17 +3401,17 @@ bool ARM64AsmParser::parseVectorList(Ope
const MCExpr *ImmVal;
if (getParser().parseExpression(ImmVal))
- return MatchOperand_ParseFail;
+ return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
if (!MCE) {
TokError("immediate value expected for vector index");
- return MatchOperand_ParseFail;
+ return false;
}
SMLoc E = getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac)) {
Error(E, "']' expected");
- return MatchOperand_ParseFail;
+ return false;
}
Parser.Lex(); // Eat right bracket token.
Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205301&r1=205300&r2=205301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Tue Apr 1 07:22:20 2014
@@ -1537,7 +1537,7 @@ static DecodeStatus DecodeUnconditionalB
if (imm & (1 << (26 - 1)))
imm |= ~((1LL << 26) - 1);
- if (!Dis->tryAddingSymbolicOperand(Addr, imm << 2, Success, 4, Inst))
+ if (!Dis->tryAddingSymbolicOperand(Addr, imm << 2, true, 4, Inst))
Inst.addOperand(MCOperand::CreateImm(imm));
return Success;
@@ -1571,7 +1571,7 @@ static DecodeStatus DecodeTestAndBranch(
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(bit));
- if (!Dis->tryAddingSymbolicOperand(Addr, dst << 2, Success, 4, Inst))
+ if (!Dis->tryAddingSymbolicOperand(Addr, dst << 2, true, 4, Inst))
Inst.addOperand(MCOperand::CreateImm(dst));
return Success;
Modified: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h?rev=205301&r1=205300&r2=205301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h Tue Apr 1 07:22:20 2014
@@ -612,16 +612,16 @@ static inline bool isAdvSIMDModImmType10
}
static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
- bool BitA = Imm & 0xff00000000000000ULL;
- bool BitB = Imm & 0x00ff000000000000ULL;
- bool BitC = Imm & 0x0000ff0000000000ULL;
- bool BitD = Imm & 0x000000ff00000000ULL;
- bool BitE = Imm & 0x00000000ff000000ULL;
- bool BitF = Imm & 0x0000000000ff0000ULL;
- bool BitG = Imm & 0x000000000000ff00ULL;
- bool BitH = Imm & 0x00000000000000ffULL;
+ uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
+ uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
+ uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
+ uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
+ uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
+ uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
+ uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
+ uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
- unsigned EncVal = BitA;
+ uint8_t EncVal = BitA;
EncVal <<= 1;
EncVal |= BitB;
EncVal <<= 1;
@@ -661,16 +661,16 @@ static inline bool isAdvSIMDModImmType11
}
static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
- bool BitA = (Imm & 0x80000000ULL);
- bool BitB = (Imm & 0x20000000ULL);
- bool BitC = (Imm & 0x01000000ULL);
- bool BitD = (Imm & 0x00800000ULL);
- bool BitE = (Imm & 0x00400000ULL);
- bool BitF = (Imm & 0x00200000ULL);
- bool BitG = (Imm & 0x00100000ULL);
- bool BitH = (Imm & 0x00080000ULL);
+ uint8_t BitA = (Imm & 0x80000000ULL) != 0;
+ uint8_t BitB = (Imm & 0x20000000ULL) != 0;
+ uint8_t BitC = (Imm & 0x01000000ULL) != 0;
+ uint8_t BitD = (Imm & 0x00800000ULL) != 0;
+ uint8_t BitE = (Imm & 0x00400000ULL) != 0;
+ uint8_t BitF = (Imm & 0x00200000ULL) != 0;
+ uint8_t BitG = (Imm & 0x00100000ULL) != 0;
+ uint8_t BitH = (Imm & 0x00080000ULL) != 0;
- unsigned EncVal = BitA;
+ uint8_t EncVal = BitA;
EncVal <<= 1;
EncVal |= BitB;
EncVal <<= 1;
@@ -710,16 +710,16 @@ static inline bool isAdvSIMDModImmType12
}
static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
- bool BitA = (Imm & 0x8000000000000000ULL);
- bool BitB = (Imm & 0x0040000000000000ULL);
- bool BitC = (Imm & 0x0020000000000000ULL);
- bool BitD = (Imm & 0x0010000000000000ULL);
- bool BitE = (Imm & 0x0008000000000000ULL);
- bool BitF = (Imm & 0x0004000000000000ULL);
- bool BitG = (Imm & 0x0002000000000000ULL);
- bool BitH = (Imm & 0x0001000000000000ULL);
+ uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
+ uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
+ uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
+ uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
+ uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
+ uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
+ uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
+ uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
- unsigned EncVal = BitA;
+ uint8_t EncVal = BitA;
EncVal <<= 1;
EncVal |= BitB;
EncVal <<= 1;
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