[llvm] r205202 - ARM64: add i64 scalar pattern for @llvm.arm64.abs

[Tim Northover]

Author: tnorthover
Date: Mon Mar 31 10:46:17 2014
New Revision: 205202

URL: http://llvm.org/viewvc/llvm-project?rev=205202&view=rev
Log:
ARM64: add i64 scalar pattern for @llvm.arm64.abs

This will be used by the Clang front-end code for vabsd_s64.

Modified:
    llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
    llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
    llvm/trunk/test/CodeGen/ARM64/vabs.ll

Modified: llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsARM64.td?rev=205202&r1=205201&r2=205202&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsARM64.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsARM64.td Mon Mar 31 10:46:17 2014
@@ -326,7 +326,7 @@ let Properties = [IntrNoMem] in {
   def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 
   // Vector Absolute Value
-  def int_arm64_neon_abs : AdvSIMD_1VectorArg_Intrinsic;
+  def int_arm64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
 
   // Vector Saturating Absolute Value
   def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td?rev=205202&r1=205201&r2=205202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrFormats.td Mon Mar 31 10:46:17 2014
@@ -5102,6 +5102,9 @@ multiclass SIMDTwoScalarD<bit U, bits<5>
                           SDPatternOperator OpNode = null_frag> {
   def v1i64       : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
     [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
+
+  def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
+            (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
 }
 
 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td?rev=205202&r1=205201&r2=205202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td Mon Mar 31 10:46:17 2014
@@ -2052,13 +2052,6 @@ defm CMLE   : SIMDCmpTwoVector<1, 0b0100
 defm CMLT   : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
 defm CNT    : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
 defm FABS   : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
-def : Pat<(v2f32 (int_arm64_neon_abs (v2f32 V64:$Rn))),
-          (FABSv2f32 V64:$Rn)>;
-def : Pat<(v4f32 (int_arm64_neon_abs (v4f32 V128:$Rn))),
-          (FABSv4f32 V128:$Rn)>;
-def : Pat<(v2f64 (int_arm64_neon_abs (v2f64 V128:$Rn))),
-          (FABSv2f64 V128:$Rn)>;
-
 
 defm FCMEQ  : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
 defm FCMGE  : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;

Modified: llvm/trunk/test/CodeGen/ARM64/vabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vabs.ll?rev=205202&r1=205201&r2=205202&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vabs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vabs.ll Mon Mar 31 10:46:17 2014
@@ -452,6 +452,13 @@ define <1 x i64> @abs_1d(<1 x i64> %A) n
   ret <1 x i64> %abs
 }
 
+define i64 @abs_1d_honestly(i64 %A) nounwind {
+; CHECK-LABEL: abs_1d_honestly:
+; CHECK: abs d0, d0
+  %abs = call i64 @llvm.arm64.neon.abs.i64(i64 %A)
+  ret i64 %abs
+}
+
 declare <8 x i8> @llvm.arm64.neon.abs.v8i8(<8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.arm64.neon.abs.v16i8(<16 x i8>) nounwind readnone
 declare <4 x i16> @llvm.arm64.neon.abs.v4i16(<4 x i16>) nounwind readnone
@@ -459,6 +466,7 @@ declare <8 x i16> @llvm.arm64.neon.abs.v
 declare <2 x i32> @llvm.arm64.neon.abs.v2i32(<2 x i32>) nounwind readnone
 declare <4 x i32> @llvm.arm64.neon.abs.v4i32(<4 x i32>) nounwind readnone
 declare <1 x i64> @llvm.arm64.neon.abs.v1i64(<1 x i64>) nounwind readnone
+declare i64 @llvm.arm64.neon.abs.i64(i64) nounwind readnone
 
 define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B,  <8 x i16>* %C) nounwind {
 ;CHECK-LABEL: sabal8h: