[llvm] r205161 - [ARM64] Fix materialization of an fp128 zero immediate. There currently

[Chandler Carruth]

Author: chandlerc
Date: Sun Mar 30 19:02:10 2014
New Revision: 205161

URL: http://llvm.org/viewvc/llvm-project?rev=205161&view=rev
Log:
[ARM64] Fix materialization of an fp128 zero immediate. There currently
is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM64/fp-imm.ll

Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=205161&r1=205160&r2=205161&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Sun Mar 30 19:02:10 2014
@@ -3879,8 +3879,9 @@ ARM64TargetLowering::isOffsetFoldingLega
 }
 
 bool ARM64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
-  // We can materialize #0.0 as fmov $Rd, XZR.
-  if (Imm.isPosZero())
+  // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
+  // FIXME: We should be able to handle f128 as well with a clever lowering.
+  if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
     return true;
 
   if (VT == MVT::f64)

Modified: llvm/trunk/test/CodeGen/ARM64/fp-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp-imm.ll?rev=205161&r1=205160&r2=205161&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp-imm.ll Sun Mar 30 19:02:10 2014
@@ -19,3 +19,14 @@ define float @bar() {
 ; CHECK-NEXT:  ret
   ret float 0x400921FB60000000
 }
+
+; CHECK: literal16
+; CHECK: .quad 0
+; CHECK: .quad 0
+define fp128 @baz() {
+; CHECK: _baz:
+; CHECK:  adrp x[[REG:[0-9]+]], lCPI2_0 at PAGE
+; CHECK:  ldr  q0, [x[[REG]], lCPI2_0 at PAGEOFF]
+; CHECK-NEXT:  ret
+  ret fp128 0xL00000000000000000000000000000000
+}