[llvm] r205091 - [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is

[Chandler Carruth]

Author: chandlerc
Date: Sat Mar 29 06:07:40 2014
New Revision: 205091

URL: http://llvm.org/viewvc/llvm-project?rev=205091&view=rev
Log:
[ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.

Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
    llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp?rev=205091&r1=205090&r2=205091&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp Sat Mar 29 06:07:40 2014
@@ -1880,7 +1880,7 @@ SDNode *ARM64DAGToDAGISel::Select(SDNode
                 .getVectorElementType()
                 .getSizeInBits()) {
     default:
-      assert("Unexpected vector element type!");
+      assert(0 && "Unexpected vector element type!");
     case 64:
       SubReg = ARM64::dsub;
       break;

Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205091&r1=205090&r2=205091&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Sat Mar 29 06:07:40 2014
@@ -230,7 +230,7 @@ getVariant(uint64_t LLVMDisassembler_Var
   case LLVMDisassembler_VariantKind_ARM64_TLVP:
   case LLVMDisassembler_VariantKind_ARM64_TLVOFF:
   default:
-    assert("bad LLVMDisassembler_VariantKind");
+    assert(0 && "bad LLVMDisassembler_VariantKind");
     return MCSymbolRefExpr::VK_None;
   }
 }

Modified: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp?rev=205091&r1=205090&r2=205091&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp Sat Mar 29 06:07:40 2014
@@ -936,7 +936,7 @@ void ARM64InstPrinter::printPostIncOpera
     else
       O << getRegisterName(Reg);
   } else
-    assert("unknown operand kind in printPostIncOperand64");
+    assert(0 && "unknown operand kind in printPostIncOperand64");
 }
 
 void ARM64InstPrinter::printPostIncOperand1(const MCInst *MI, unsigned OpNo,