[llvm] r205067 - [x86] Fix printing of register operands with q modifier.

[Akira Hatanaka]

Author: ahatanak
Date: Fri Mar 28 18:28:07 2014
New Revision: 205067

URL: http://llvm.org/viewvc/llvm-project?rev=205067&view=rev
Log:
[x86] Fix printing of register operands with q modifier.

Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.

<rdar://problem/14653996>

Added:
    llvm/trunk/test/CodeGen/X86/inline-asm-modifier-q.ll
Modified:
    llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp

Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=205067&r1=205066&r2=205067&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Fri Mar 28 18:28:07 2014
@@ -363,9 +363,11 @@ static bool printAsmMRegister(X86AsmPrin
   case 'k': // Print SImode register
     Reg = getX86SubSuperRegister(Reg, MVT::i32);
     break;
-  case 'q': // Print DImode register
-    // FIXME: gcc will actually print e instead of r for 32-bit.
-    Reg = getX86SubSuperRegister(Reg, MVT::i64);
+  case 'q':
+    // Print 64-bit register names if 64-bit integer registers are available.
+    // Otherwise, print 32-bit register names.
+    MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
+    Reg = getX86SubSuperRegister(Reg, Ty);
     break;
   }
 

Added: llvm/trunk/test/CodeGen/X86/inline-asm-modifier-q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-modifier-q.ll?rev=205067&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-modifier-q.ll (added)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-modifier-q.ll Fri Mar 28 18:28:07 2014
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s
+
+; If the target does not have 64-bit integer registers, emit 32-bit register
+; names.
+
+; CHECK: movq (%e{{[abcd]}}x, %ebx, 4)
+
+define void @q_modifier(i32* %p) {
+entry:
+  tail call void asm sideeffect "movq (${0:q}, %ebx, 4), %mm0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %p)
+  ret void
+}