[llvm] r205028 - Parse .gpdword and convert another llc -filetype=obj test.
Rafael Espindola
rafael.espindola at gmail.com
Fri Mar 28 11:50:26 PDT 2014
Author: rafael
Date: Fri Mar 28 13:50:26 2014
New Revision: 205028
URL: http://llvm.org/viewvc/llvm-project?rev=205028&view=rev
Log:
Parse .gpdword and convert another llc -filetype=obj test.
Added:
llvm/trunk/test/MC/Mips/elf-gprel-32-64.s
Removed:
llvm/trunk/test/MC/Mips/elf-gprel-32-64.ll
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/test/MC/Mips/do_switch3.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=205028&r1=205027&r2=205028&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Fri Mar 28 13:50:26 2014
@@ -212,6 +212,7 @@ class MipsAsmParser : public MCTargetAsm
bool parseDataDirective(unsigned Size, SMLoc L);
bool parseDirectiveGpWord();
+ bool parseDirectiveGpdWord();
MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
@@ -2715,6 +2716,22 @@ bool MipsAsmParser::parseDirectiveGpWord
return false;
}
+/// parseDirectiveGpdWord
+/// ::= .gpdword local_sym
+bool MipsAsmParser::parseDirectiveGpdWord() {
+ const MCExpr *Value;
+ // EmitGPRel64Value requires an expression, so we are using base class
+ // method to evaluate the expression.
+ if (getParser().parseExpression(Value))
+ return true;
+ getParser().getStreamer().EmitGPRel64Value(Value);
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(getLexer().getLoc(), "unexpected token in directive");
+ Parser.Lex(); // Eat EndOfStatement token.
+ return false;
+}
+
bool MipsAsmParser::parseDirectiveOption() {
// Get the option token.
AsmToken Tok = Parser.getTok();
@@ -2798,11 +2815,15 @@ bool MipsAsmParser::ParseDirective(AsmTo
}
if (IDVal == ".gpword") {
- // Ignore this directive for now.
parseDirectiveGpWord();
return false;
}
+ if (IDVal == ".gpdword") {
+ parseDirectiveGpdWord();
+ return false;
+ }
+
if (IDVal == ".word") {
parseDataDirective(4, DirectiveID.getLoc());
return false;
Modified: llvm/trunk/test/MC/Mips/do_switch3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/do_switch3.s?rev=205028&r1=205027&r2=205028&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/do_switch3.s (original)
+++ llvm/trunk/test/MC/Mips/do_switch3.s Fri Mar 28 13:50:26 2014
@@ -73,10 +73,10 @@ $tmp0:
.section .rodata,"a", at progbits
.align 3
$JTI0_0:
-// .gpdword ($BB0_3)
-// .gpdword ($BB0_4)
-// .gpdword ($BB0_5)
-// .gpdword ($BB0_6)
+ .gpdword ($BB0_3)
+ .gpdword ($BB0_4)
+ .gpdword ($BB0_5)
+ .gpdword ($BB0_6)
.text
Removed: llvm/trunk/test/MC/Mips/elf-gprel-32-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/elf-gprel-32-64.ll?rev=205027&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/elf-gprel-32-64.ll (original)
+++ llvm/trunk/test/MC/Mips/elf-gprel-32-64.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 %s -o - \
-; RUN: | llvm-readobj -r \
-; RUN: | FileCheck %s
-
-define i32 @test(i32 %c) nounwind {
-entry:
- switch i32 %c, label %sw.default [
- i32 0, label %sw.bb
- i32 1, label %sw.bb2
- i32 2, label %sw.bb5
- i32 3, label %sw.bb8
- ]
-
-sw.bb:
- br label %return
-sw.bb2:
- br label %return
-sw.bb5:
- br label %return
-sw.bb8:
- br label %return
-sw.default:
- br label %return
-
-return:
- %retval.0 = phi i32 [ -1, %sw.default ], [ 7, %sw.bb8 ], [ 2, %sw.bb5 ], [ 3, %sw.bb2 ], [ 1, %sw.bb ]
- ret i32 %retval.0
-}
-
-; Check that the appropriate relocations were created.
-
-; R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
-; CHECK: Relocations [
-; CHECK: Section ({{[a-z0-9]+}}) .rela.rodata {
-; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
-; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
-; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
-; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
-; CHECK-NEXT: }
-; CHECK-NEXT: ]
Added: llvm/trunk/test/MC/Mips/elf-gprel-32-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/elf-gprel-32-64.s?rev=205028&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/elf-gprel-32-64.s (added)
+++ llvm/trunk/test/MC/Mips/elf-gprel-32-64.s Fri Mar 28 13:50:26 2014
@@ -0,0 +1,83 @@
+// RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - \
+// RUN: | llvm-readobj -r \
+// RUN: | FileCheck %s
+
+// Check that the appropriate relocations were created.
+
+// R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
+// CHECK: Relocations [
+// CHECK: Section ({{[a-z0-9]+}}) .rela.rodata {
+// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
+// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
+// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
+// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE
+// CHECK-NEXT: }
+// CHECK-NEXT: ]
+
+ .text
+ .abicalls
+ .section .mdebug.abi64,"", at progbits
+ .file "/home/espindola/llvm/llvm/test/MC/Mips/elf-gprel-32-64.ll"
+ .text
+ .globl test
+ .align 3
+ .type test, at function
+ .set nomips16
+ .ent test
+test: # @test
+ .frame $sp,0,$ra
+ .mask 0x00000000,0
+ .fmask 0x00000000,0
+ .set noreorder
+ .set nomacro
+ .set noat
+# BB#0: # %entry
+ lui $1, %hi(%neg(%gp_rel(test)))
+ daddu $2, $1, $25
+ sltiu $1, $4, 4
+ dsll $3, $4, 32
+ bnez $1, $BB0_2
+ nop
+$BB0_1: # %sw.default
+ b $BB0_3
+ addiu $2, $zero, -1
+$BB0_2: # %entry
+ daddiu $1, $2, %lo(%neg(%gp_rel(test)))
+ dsrl $3, $3, 32
+ daddiu $4, $zero, 8
+ dmult $3, $4
+ mflo $3
+ ld $4, %got_page($JTI0_0)($1)
+ daddu $3, $3, $4
+ ld $3, %got_ofst($JTI0_0)($3)
+ daddu $1, $3, $1
+ jr $1
+ addiu $2, $zero, 1
+$BB0_3: # %return
+ jr $ra
+ nop
+$BB0_4: # %sw.bb2
+ jr $ra
+ addiu $2, $zero, 3
+$BB0_5: # %sw.bb5
+ jr $ra
+ addiu $2, $zero, 2
+$BB0_6: # %sw.bb8
+ jr $ra
+ addiu $2, $zero, 7
+ .set at
+ .set macro
+ .set reorder
+ .end test
+$tmp0:
+ .size test, ($tmp0)-test
+ .section .rodata,"a", at progbits
+ .align 3
+$JTI0_0:
+ .gpdword ($BB0_3)
+ .gpdword ($BB0_4)
+ .gpdword ($BB0_5)
+ .gpdword ($BB0_6)
+
+
+ .text
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