[PATCH][mips] Add more Octeon cnMips instructions
Kai Nacke
kai.nacke at redstar.de
Thu Mar 27 11:06:55 PDT 2014
Somehow the latest test case was not committed in my tree. This patch
contains the current test case. Sorry.
Regards,
Kai
On 27.03.2014 17:56, Kai Nacke wrote:
> Hi all!
>
> This patch adds the cnMips instructions ext/ext32/cins/cins32.
> It also changes baddud/pop/dpop to accept the two operand version and
> adds a simple pattern to generate baddu. Test cases are included.
>
> Please review.
>
> Regards,
> Kai
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
-------------- next part --------------
>From f984292a364bb359dcc08a1b694ac27f7b9d25a1 Mon Sep 17 00:00:00 2001
From: kai <kai at redstar.de>
Date: Thu, 20 Mar 2014 13:30:28 +0100
Subject: [PATCH] Add more Octeon cnMips instructions
Adds the instructions ext/ext32/cins/cins32.
It also changes baddud/pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
---
lib/Target/Mips/Mips64InstrInfo.td | 41 +++++++++++++++++++++++++++---------
lib/Target/Mips/MipsISelLowering.cpp | 4 ++++
lib/Target/Mips/MipsISelLowering.h | 6 ++++++
lib/Target/Mips/MipsInstrFormats.td | 16 ++++++++++++++
lib/Target/Mips/MipsInstrInfo.td | 7 ++++++
test/CodeGen/Mips/octeon.ll | 14 ++++++++++++
test/MC/Mips/octeon-instructions.s | 32 ++++++++++++++++++++++++++--
7 files changed, 108 insertions(+), 12 deletions(-)
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index e44a52e..edfe5a7 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -234,29 +234,43 @@ let Predicates = [HasCnMips] in {
class Count1s<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr>;
+ [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
+ let TwoOperandAliasConstraint = "$rd = $rs";
+}
+
+class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
+ InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
+ !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
+ [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
+ NoItinerary, FrmR, opstr> {
+ let TwoOperandAliasConstraint = "$rt = $rs";
+}
class SetCC64_R<string opstr, PatFrag cond_op> :
InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
- II_SEQ_SNE, FrmR, opstr>;
+ II_SEQ_SNE, FrmR, opstr> {
+ let TwoOperandAliasConstraint = "$rd = $rs";
+}
// Unsigned Byte Add
-def BADDu : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
- "baddu\t$rd, $rs, $rt",
- [(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs,
- GPR64Opnd:$rt), 255))],
- II_BADDU, FrmR, "baddu">, ADD_FM<0x1c, 0x28> {
- let isCommutable = 1;
- let isReMaterializable = 1;
-}
+def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU, MipsBaddu>,
+ ADD_FM<0x1c, 0x28>;
// Multiply Doubleword to GPR
let Defs = [HI0, LO0, P0, P1, P2] in
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
ADD_FM<0x1c, 0x03>;
+// Extract a signed bit field /+32
+def EXTS : ExtsCins<"exts", MipsExtS>, EXTS_FM<0x3a>;
+def EXTS32: ExtsCins<"exts32", MipsExtS32>, EXTS_FM<0x3b>;
+
+// Clear and insert a bit field /+32
+def CINS : ExtsCins<"cins", MipsCIns>, EXTS_FM<0x32>;
+def CINS32: ExtsCins<"cins32", MipsCIns32>, EXTS_FM<0x33>;
+
// Count Ones in a Word/Doubleword
def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
@@ -267,6 +281,13 @@ def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
}
}
+
+let Predicates = [HasCnMips] in {
+
+def : MipsPat<(and (add GPR64:$rs, GPR64:$rt), 255),
+ (BADDu GPR64:$rs, GPR64:$rt)>;
+}
+
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 186b9c3..afb2ed0 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -146,7 +146,11 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
case MipsISD::Wrapper: return "MipsISD::Wrapper";
case MipsISD::Sync: return "MipsISD::Sync";
case MipsISD::Ext: return "MipsISD::Ext";
+ case MipsISD::ExtS: return "MipsISD::ExtS";
+ case MipsISD::ExtS32: return "MipsISD::ExtS32";
case MipsISD::Ins: return "MipsISD::Ins";
+ case MipsISD::CIns: return "MipsISD::CIns";
+ case MipsISD::CIns32: return "MipsISD::CIns32";
case MipsISD::LWL: return "MipsISD::LWL";
case MipsISD::LWR: return "MipsISD::LWR";
case MipsISD::SWL: return "MipsISD::SWL";
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 6f60a1e..81f4fed 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -104,8 +104,14 @@ namespace llvm {
Sync,
+ Baddu, // cnMips
+
Ext,
+ ExtS, // cnMips
+ ExtS32, // cnMips
Ins,
+ CIns, // cnMips
+ CIns32, // cnMips
// EXTR.W instrinsic nodes.
EXTP,
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index 09fcd5e..79c5d26 100644
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -489,6 +489,22 @@ class WAIT_FM : StdArch {
let Inst{5-0} = 0x20;
}
+class EXTS_FM<bits<6> funct> : StdArch {
+ bits<5> rt;
+ bits<5> rs;
+ bits<5> pos;
+ bits<5> lenm1;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0x1c;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = rt;
+ let Inst{15-11} = lenm1;
+ let Inst{10-6} = pos;
+ let Inst{5-0} = funct;
+}
+
class POP_FM<bits<6> funct> : StdArch {
bits<5> rd;
bits<5> rs;
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 1584d29..648ee6a 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -143,6 +143,13 @@ def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+// Nodes for cnMips instructions
+def MipsBaddu : SDNode<"MipsISD::Baddu", SDTIntBinOp>;
+def MipsExtS : SDNode<"MipsISD::ExtS", SDT_Ext>;
+def MipsExtS32 : SDNode<"MipsISD::ExtS32", SDT_Ext>;
+def MipsCIns : SDNode<"MipsISD::CIns", SDT_Ext>;
+def MipsCIns32 : SDNode<"MipsISD::CIns", SDT_Ext>;
+
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll
index 092938a..d5ff9bd 100644
--- a/test/CodeGen/Mips/octeon.ll
+++ b/test/CodeGen/Mips/octeon.ll
@@ -1,6 +1,20 @@
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON
; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64
+define i64 @addi64(i64 %a, i64 %b) nounwind {
+entry:
+; OCTEON-LABEL: addi64:
+; OCTEON: jr $ra
+; OCTEON: baddu $2, $4, $5
+; MIPS64-LABEL: addi64:
+; MIPS64: daddu
+; MIPS64: jr
+; MIPS64: andi
+ %add = add i64 %a, %b
+ %and = and i64 %add, 255
+ ret i64 %and
+}
+
define i64 @mul(i64 %a, i64 %b) nounwind {
entry:
; OCTEON-LABEL: mul:
diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s
index 8c0342a..77527b9 100644
--- a/test/MC/Mips/octeon-instructions.s
+++ b/test/MC/Mips/octeon-instructions.s
@@ -2,24 +2,52 @@
# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
-# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
+# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28]
+# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2]
+# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72]
+# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3]
+# CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73]
# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03]
# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03]
+# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03]
+# CHECK: dmul $21, $21, $25 # encoding: [0x72,0xb9,0xa8,0x03]
# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d]
# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d]
+# CHECK: dpop $12, $12 # encoding: [0x71,0x80,0x60,0x2d]
+# CHECK: exts $4, $25, 27, 15 # encoding: [0x73,0x24,0x7e,0xfa]
+# CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a]
+# CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb]
+# CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb]
# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c]
# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c]
+# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c]
# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
+# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a]
# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
+# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b]
baddu $9, $6, $7
baddu $17, $18, $19
- dmul $9, $6
+ baddu $2, $3
+ cins $25, $10, 22, 2
+ cins $9, 17, 29
+ cins32 $15, $2, 18, 8
+ cins32 $22, 9, 22
dmul $9, $6, $7
dmul $19, $24, $25
+ dmul $9, $6
+ dmul $21, $25
dpop $9, $6
dpop $15, $22
+ dpop $12
+ exts $4, $25, 27, 15
+ exts $15, 17, 6
+ exts32 $4, $13, 10, 8
+ exts32 $15, 11, 20
pop $9, $6
pop $8, $19
+ pop $2
seq $25, $23, $24
+ seq $6, $24
sne $25, $23, $24
+ sne $23, $20
--
1.8.0.msysgit.0
More information about the llvm-commits
mailing list