[PATCH] R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp

Tom Stellard tom at stellard.net
Tue Mar 25 10:46:54 PDT 2014


On Tue, Mar 25, 2014 at 10:45:47AM -0700, Matt Arsenault wrote:
> On 03/25/2014 10:42 AM, Tom Stellard wrote:
> >On Tue, Mar 25, 2014 at 09:59:26AM -0700, Matt Arsenault wrote:
> >>http://llvm-reviews.chandlerc.com/D3183
> >>
> >>Files:
> >>   lib/Target/R600/AMDGPUISelLowering.cpp
> >>   lib/Target/R600/AMDGPUISelLowering.h
> >>   lib/Target/R600/AMDILISelLowering.cpp
> >>
> >>Index: lib/Target/R600/AMDGPUISelLowering.cpp
> >>===================================================================
> >>--- lib/Target/R600/AMDGPUISelLowering.cpp
> >>+++ lib/Target/R600/AMDGPUISelLowering.cpp
> >>@@ -1591,6 +1591,33 @@
> >>    }
> >>  }
> >>+void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
> >>+  const SDValue Op,
> >>+  APInt &KnownZero,
> >>+  APInt &KnownOne,
> >>+  const SelectionDAG &DAG,
> >>+  unsigned Depth) const {
> >>+  APInt KnownZero2;
> >>+  APInt KnownOne2;
> >>+  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
> >>+  switch (Op.getOpcode()) {
> >>+  default:
> >>+    break;
> >>+  case ISD::SELECT_CC:
> >>+    // FIXME: Why is this here? This isn't a target node. It doesn't even seem
> >>+    // to be inspecting the right operands.
> >Let's just delete this function then.
> >
> >-Tom
> I have another later patch that does implement this function for
> real target nodes
> 

Ok, but let's remove the SELECT_CC case, because it shouldn't be here.

-Tom

> >>+    DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth + 1);
> >>+    DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2);
> >>+    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
> >>+    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
> >>+
> >>+    // Only known if known in both the LHS and RHS.
> >>+    KnownOne &= KnownOne2;
> >>+    KnownZero &= KnownZero2;
> >>+    break;
> >>+  }
> >>+}
> >>+
> >>  SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
> >>                                                  DAGCombinerInfo &DCI) const {
> >>    SelectionDAG &DAG = DCI.DAG;
> >>Index: lib/Target/R600/AMDGPUISelLowering.h
> >>===================================================================
> >>--- lib/Target/R600/AMDGPUISelLowering.h
> >>+++ lib/Target/R600/AMDGPUISelLowering.h
> >>@@ -136,9 +136,6 @@
> >>      return N;
> >>    }
> >>-// Functions defined in AMDILISelLowering.cpp
> >>-public:
> >>-
> >>    /// \brief Determine which of the bits specified in \p Mask are known to be
> >>    /// either zero or one and return them in the \p KnownZero and \p KnownOne
> >>    /// bitsets.
> >>@@ -146,8 +143,10 @@
> >>                                                APInt &KnownZero,
> >>                                                APInt &KnownOne,
> >>                                                const SelectionDAG &DAG,
> >>-                                              unsigned Depth = 0) const;
> >>+                                              unsigned Depth = 0) const override;
> >>+// Functions defined in AMDILISelLowering.cpp
> >>+public:
> >>    virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
> >>                                    const CallInst &I, unsigned Intrinsic) const;
> >>Index: lib/Target/R600/AMDILISelLowering.cpp
> >>===================================================================
> >>--- lib/Target/R600/AMDILISelLowering.cpp
> >>+++ lib/Target/R600/AMDILISelLowering.cpp
> >>@@ -243,41 +243,6 @@
> >>  // be zero. Op is expected to be a target specific node. Used by DAG
> >>  // combiner.
> >>-void
> >>-AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
> >>-    const SDValue Op,
> >>-    APInt &KnownZero,
> >>-    APInt &KnownOne,
> >>-    const SelectionDAG &DAG,
> >>-    unsigned Depth) const {
> >>-  APInt KnownZero2;
> >>-  APInt KnownOne2;
> >>-  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
> >>-  switch (Op.getOpcode()) {
> >>-    default: break;
> >>-    case ISD::SELECT_CC:
> >>-             DAG.ComputeMaskedBits(
> >>-                 Op.getOperand(1),
> >>-                 KnownZero,
> >>-                 KnownOne,
> >>-                 Depth + 1
> >>-                 );
> >>-             DAG.ComputeMaskedBits(
> >>-                 Op.getOperand(0),
> >>-                 KnownZero2,
> >>-                 KnownOne2
> >>-                 );
> >>-             assert((KnownZero & KnownOne) == 0
> >>-                 && "Bits known to be one AND zero?");
> >>-             assert((KnownZero2 & KnownOne2) == 0
> >>-                 && "Bits known to be one AND zero?");
> >>-             // Only known if known in both the LHS and RHS
> >>-             KnownOne &= KnownOne2;
> >>-             KnownZero &= KnownZero2;
> >>-             break;
> >>-  };
> >>-}
> >>-
> >>  //===----------------------------------------------------------------------===//
> >>  //                           Other Lowering Hooks
> >>  //===----------------------------------------------------------------------===//
> >>Index: lib/Target/R600/AMDGPUISelLowering.cpp
> >>===================================================================
> >>--- lib/Target/R600/AMDGPUISelLowering.cpp
> >>+++ lib/Target/R600/AMDGPUISelLowering.cpp
> >>@@ -1591,6 +1591,33 @@
> >>    }
> >>  }
> >>+void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
> >>+  const SDValue Op,
> >>+  APInt &KnownZero,
> >>+  APInt &KnownOne,
> >>+  const SelectionDAG &DAG,
> >>+  unsigned Depth) const {
> >>+  APInt KnownZero2;
> >>+  APInt KnownOne2;
> >>+  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
> >>+  switch (Op.getOpcode()) {
> >>+  default:
> >>+    break;
> >>+  case ISD::SELECT_CC:
> >>+    // FIXME: Why is this here? This isn't a target node. It doesn't even seem
> >>+    // to be inspecting the right operands.
> >>+    DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth + 1);
> >>+    DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2);
> >>+    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
> >>+    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
> >>+
> >>+    // Only known if known in both the LHS and RHS.
> >>+    KnownOne &= KnownOne2;
> >>+    KnownZero &= KnownZero2;
> >>+    break;
> >>+  }
> >>+}
> >>+
> >>  SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
> >>                                                  DAGCombinerInfo &DCI) const {
> >>    SelectionDAG &DAG = DCI.DAG;
> >>Index: lib/Target/R600/AMDGPUISelLowering.h
> >>===================================================================
> >>--- lib/Target/R600/AMDGPUISelLowering.h
> >>+++ lib/Target/R600/AMDGPUISelLowering.h
> >>@@ -136,9 +136,6 @@
> >>      return N;
> >>    }
> >>-// Functions defined in AMDILISelLowering.cpp
> >>-public:
> >>-
> >>    /// \brief Determine which of the bits specified in \p Mask are known to be
> >>    /// either zero or one and return them in the \p KnownZero and \p KnownOne
> >>    /// bitsets.
> >>@@ -146,8 +143,10 @@
> >>                                                APInt &KnownZero,
> >>                                                APInt &KnownOne,
> >>                                                const SelectionDAG &DAG,
> >>-                                              unsigned Depth = 0) const;
> >>+                                              unsigned Depth = 0) const override;
> >>+// Functions defined in AMDILISelLowering.cpp
> >>+public:
> >>    virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
> >>                                    const CallInst &I, unsigned Intrinsic) const;
> >>Index: lib/Target/R600/AMDILISelLowering.cpp
> >>===================================================================
> >>--- lib/Target/R600/AMDILISelLowering.cpp
> >>+++ lib/Target/R600/AMDILISelLowering.cpp
> >>@@ -243,41 +243,6 @@
> >>  // be zero. Op is expected to be a target specific node. Used by DAG
> >>  // combiner.
> >>-void
> >>-AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
> >>-    const SDValue Op,
> >>-    APInt &KnownZero,
> >>-    APInt &KnownOne,
> >>-    const SelectionDAG &DAG,
> >>-    unsigned Depth) const {
> >>-  APInt KnownZero2;
> >>-  APInt KnownOne2;
> >>-  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything
> >>-  switch (Op.getOpcode()) {
> >>-    default: break;
> >>-    case ISD::SELECT_CC:
> >>-             DAG.ComputeMaskedBits(
> >>-                 Op.getOperand(1),
> >>-                 KnownZero,
> >>-                 KnownOne,
> >>-                 Depth + 1
> >>-                 );
> >>-             DAG.ComputeMaskedBits(
> >>-                 Op.getOperand(0),
> >>-                 KnownZero2,
> >>-                 KnownOne2
> >>-                 );
> >>-             assert((KnownZero & KnownOne) == 0
> >>-                 && "Bits known to be one AND zero?");
> >>-             assert((KnownZero2 & KnownOne2) == 0
> >>-                 && "Bits known to be one AND zero?");
> >>-             // Only known if known in both the LHS and RHS
> >>-             KnownOne &= KnownOne2;
> >>-             KnownZero &= KnownZero2;
> >>-             break;
> >>-  };
> >>-}
> >>-
> >>  //===----------------------------------------------------------------------===//
> >>  //                           Other Lowering Hooks
> >>  //===----------------------------------------------------------------------===//
> >>_______________________________________________
> >>llvm-commits mailing list
> >>llvm-commits at cs.uiuc.edu
> >>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> 
> 



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