[PATCH] Fix assertion with a trunc store to an i1 vector.

Matt Arsenault Matthew.Arsenault at amd.com
Mon Mar 24 14:09:02 PDT 2014


The getZeroExtendInReg complains because the type is not a scalar.
This only half fixes the problem I ran into, since it ends up creating 
an illegal vector operation, but I don't need this anymore.

http://llvm-reviews.chandlerc.com/D3163

Files:
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -773,9 +773,16 @@
         // Promote to a byte-sized store with upper bits zero if not
         // storing an integral number of bytes.  For example, promote
         // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
+
+        EVT ScalarStVT = StVT.getScalarType();
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
-                                    StVT.getStoreSizeInBits());
-        Value = DAG.getZeroExtendInReg(Value, dl, StVT);
+                                    ScalarStVT.getStoreSizeInBits());
+        if (StVT.isVector()) {
+          NVT = EVT::getVectorVT(*DAG.getContext(), NVT,
+                                 StVT.getVectorNumElements());
+        }
+
+        Value = DAG.getZeroExtendInReg(Value, dl, ScalarStVT);
         SDValue Result =
           DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
                             NVT, isVolatile, isNonTemporal, Alignment,
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