[llvm] r204560 - remove a bunch of unused private methods
Eric Christopher
echristo at gmail.com
Sun Mar 23 20:09:08 PDT 2014
On Sun, Mar 23, 2014 at 6:34 PM, David Blaikie <dblaikie at gmail.com> wrote:
> On Sun, Mar 23, 2014 at 10:09 AM, Nuno Lopes <nunoplopes at sapo.pt> wrote:
>> Author: nlopes
>> Date: Sun Mar 23 12:09:26 2014
>> New Revision: 204560
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=204560&view=rev
>> Log:
>> remove a bunch of unused private methods
>> found with a smarter version of -Wunused-member-function that I'm playwing with.
>
> Just out of curiosity - in what way are you making this warning smarter?
See his post to cfe :)
-eric
>
>> Appologies in advance if I removed someone's WIP code.
>>
>> include/llvm/CodeGen/MachineSSAUpdater.h | 1
>> include/llvm/IR/DebugInfo.h | 3
>> lib/CodeGen/MachineSSAUpdater.cpp | 10 --
>> lib/CodeGen/PostRASchedulerList.cpp | 1
>> lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 --
>> lib/IR/DebugInfo.cpp | 12 --
>> lib/MC/MCAsmStreamer.cpp | 2
>> lib/Support/YAMLParser.cpp | 39 ---------
>> lib/TableGen/TGParser.cpp | 16 ---
>> lib/TableGen/TGParser.h | 1
>> lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 --
>> lib/Target/ARM/ARMCodeEmitter.cpp | 12 --
>> lib/Target/ARM/ARMFastISel.cpp | 84 --------------------
>> lib/Target/Mips/MipsCodeEmitter.cpp | 11 --
>> lib/Target/Mips/MipsConstantIslandPass.cpp | 12 --
>> lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 -----
>> lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2
>> lib/Target/PowerPC/PPCFastISel.cpp | 1
>> lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2
>> lib/Transforms/Instrumentation/BoundsChecking.cpp | 2
>> lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1
>> lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 -
>> lib/Transforms/Scalar/SCCP.cpp | 1
>> utils/TableGen/CodeEmitterGen.cpp | 2
>> 24 files changed, 2 insertions(+), 261 deletions(-)
>>
>> Modified:
>> llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h
>> llvm/trunk/include/llvm/IR/DebugInfo.h
>> llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
>> llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
>> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>> llvm/trunk/lib/IR/DebugInfo.cpp
>> llvm/trunk/lib/MC/MCAsmStreamer.cpp
>> llvm/trunk/lib/Support/YAMLParser.cpp
>> llvm/trunk/lib/TableGen/TGParser.cpp
>> llvm/trunk/lib/TableGen/TGParser.h
>> llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>> llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
>> llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
>> llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
>> llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
>> llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp
>> llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp
>> llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
>> llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
>> llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
>>
>> Modified: llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/MachineSSAUpdater.h Sun Mar 23 12:09:26 2014
>> @@ -105,7 +105,6 @@ public:
>> void RewriteUse(MachineOperand &U);
>>
>> private:
>> - void ReplaceRegWith(unsigned OldReg, unsigned NewReg);
>> unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB);
>>
>> void operator=(const MachineSSAUpdater&) LLVM_DELETED_FUNCTION;
>>
>> Modified: llvm/trunk/include/llvm/IR/DebugInfo.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/DebugInfo.h?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/IR/DebugInfo.h (original)
>> +++ llvm/trunk/include/llvm/IR/DebugInfo.h Sun Mar 23 12:09:26 2014
>> @@ -854,9 +854,6 @@ private:
>> /// processType - Process DIType.
>> void processType(DIType DT);
>>
>> - /// processLexicalBlock - Process DILexicalBlock.
>> - void processLexicalBlock(DILexicalBlock LB);
>> -
>> /// processSubprogram - Process DISubprogram.
>> void processSubprogram(DISubprogram SP);
>>
>>
>> Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Sun Mar 23 12:09:26 2014
>> @@ -230,16 +230,6 @@ void MachineSSAUpdater::RewriteUse(Machi
>> U.setReg(NewVR);
>> }
>>
>> -void MachineSSAUpdater::ReplaceRegWith(unsigned OldReg, unsigned NewReg) {
>> - MRI->replaceRegWith(OldReg, NewReg);
>> -
>> - AvailableValsTy &AvailableVals = getAvailableVals(AV);
>> - for (DenseMap<MachineBasicBlock*, unsigned>::iterator
>> - I = AvailableVals.begin(), E = AvailableVals.end(); I != E; ++I)
>> - if (I->second == OldReg)
>> - I->second = NewReg;
>> -}
>> -
>> /// SSAUpdaterTraits<MachineSSAUpdater> - Traits for the SSAUpdaterImpl
>> /// template, specialized for MachineSSAUpdater.
>> namespace llvm {
>>
>> Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Sun Mar 23 12:09:26 2014
>> @@ -175,7 +175,6 @@ namespace {
>> void ReleaseSuccessors(SUnit *SU);
>> void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
>> void ListScheduleTopDown();
>> - void StartBlockForKills(MachineBasicBlock *BB);
>>
>> void dumpSchedule() const;
>> void emitNoop(unsigned CurCycle);
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Mar 23 12:09:26 2014
>> @@ -627,16 +627,6 @@ namespace {
>> }
>> }
>>
>> - /// areValueTypesLegal - Return true if types of all the values are legal.
>> - bool areValueTypesLegal(const TargetLowering &TLI) {
>> - for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
>> - MVT RegisterVT = RegVTs[Value];
>> - if (!TLI.isTypeLegal(RegisterVT))
>> - return false;
>> - }
>> - return true;
>> - }
>> -
>> /// append - Add the specified values to this one.
>> void append(const RegsForValue &RHS) {
>> ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
>>
>> Modified: llvm/trunk/lib/IR/DebugInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/DebugInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/IR/DebugInfo.cpp (original)
>> +++ llvm/trunk/lib/IR/DebugInfo.cpp Sun Mar 23 12:09:26 2014
>> @@ -1087,18 +1087,6 @@ void DebugInfoFinder::processScope(DISco
>> }
>> }
>>
>> -/// processLexicalBlock
>> -void DebugInfoFinder::processLexicalBlock(DILexicalBlock LB) {
>> - DIScope Context = LB.getContext();
>> - if (Context.isLexicalBlock())
>> - return processLexicalBlock(DILexicalBlock(Context));
>> - else if (Context.isLexicalBlockFile()) {
>> - DILexicalBlockFile DBF = DILexicalBlockFile(Context);
>> - return processLexicalBlock(DILexicalBlock(DBF.getScope()));
>> - } else
>> - return processSubprogram(DISubprogram(Context));
>> -}
>> -
>> /// processSubprogram - Process DISubprogram.
>> void DebugInfoFinder::processSubprogram(DISubprogram SP) {
>> if (!addSubprogram(SP))
>>
>> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
>> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Sun Mar 23 12:09:26 2014
>> @@ -59,8 +59,6 @@ private:
>>
>> DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap;
>>
>> - bool needsSet(const MCExpr *Value);
>> -
>> void EmitRegisterName(int64_t Register);
>> void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
>> void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override;
>>
>> Modified: llvm/trunk/lib/Support/YAMLParser.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/YAMLParser.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Support/YAMLParser.cpp (original)
>> +++ llvm/trunk/lib/Support/YAMLParser.cpp Sun Mar 23 12:09:26 2014
>> @@ -378,9 +378,6 @@ private:
>> /// sequence of ns-uri-char.
>> StringRef scan_ns_uri_char();
>>
>> - /// @brief Scan ns-plain-one-line[133] starting at \a Cur.
>> - StringRef scan_ns_plain_one_line();
>> -
>> /// @brief Consume a minimal well-formed code unit subsequence starting at
>> /// \a Cur. Return false if it is not the same Unicode scalar value as
>> /// \a Expected. This updates \a Column.
>> @@ -873,42 +870,6 @@ StringRef Scanner::scan_ns_uri_char() {
>> return StringRef(Start, Current - Start);
>> }
>>
>> -StringRef Scanner::scan_ns_plain_one_line() {
>> - StringRef::iterator start = Current;
>> - // The first character must already be verified.
>> - ++Current;
>> - while (true) {
>> - if (Current == End) {
>> - break;
>> - } else if (*Current == ':') {
>> - // Check if the next character is a ns-char.
>> - if (Current + 1 == End)
>> - break;
>> - StringRef::iterator i = skip_ns_char(Current + 1);
>> - if (Current + 1 != i) {
>> - Current = i;
>> - Column += 2; // Consume both the ':' and ns-char.
>> - } else
>> - break;
>> - } else if (*Current == '#') {
>> - // Check if the previous character was a ns-char.
>> - // The & 0x80 check is to check for the trailing byte of a utf-8
>> - if (*(Current - 1) & 0x80 || skip_ns_char(Current - 1) == Current) {
>> - ++Current;
>> - ++Column;
>> - } else
>> - break;
>> - } else {
>> - StringRef::iterator i = skip_nb_char(Current);
>> - if (i == Current)
>> - break;
>> - Current = i;
>> - ++Column;
>> - }
>> - }
>> - return StringRef(start, Current - start);
>> -}
>> -
>> bool Scanner::consume(uint32_t Expected) {
>> if (Expected >= 0x80)
>> report_fatal_error("Not dealing with this yet");
>>
>> Modified: llvm/trunk/lib/TableGen/TGParser.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/TableGen/TGParser.cpp (original)
>> +++ llvm/trunk/lib/TableGen/TGParser.cpp Sun Mar 23 12:09:26 2014
>> @@ -722,22 +722,6 @@ RecTy *TGParser::ParseType() {
>> }
>> }
>>
>> -/// ParseIDValue - Parse an ID as a value and decode what it means.
>> -///
>> -/// IDValue ::= ID [def local value]
>> -/// IDValue ::= ID [def template arg]
>> -/// IDValue ::= ID [multiclass local value]
>> -/// IDValue ::= ID [multiclass template argument]
>> -/// IDValue ::= ID [def name]
>> -///
>> -Init *TGParser::ParseIDValue(Record *CurRec, IDParseMode Mode) {
>> - assert(Lex.getCode() == tgtok::Id && "Expected ID in ParseIDValue");
>> - std::string Name = Lex.getCurStrVal();
>> - SMLoc Loc = Lex.getLoc();
>> - Lex.Lex();
>> - return ParseIDValue(CurRec, Name, Loc);
>> -}
>> -
>> /// ParseIDValue - This is just like ParseIDValue above, but it assumes the ID
>> /// has already been read.
>> Init *TGParser::ParseIDValue(Record *CurRec,
>>
>> Modified: llvm/trunk/lib/TableGen/TGParser.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.h?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/TableGen/TGParser.h (original)
>> +++ llvm/trunk/lib/TableGen/TGParser.h Sun Mar 23 12:09:26 2014
>> @@ -167,7 +167,6 @@ private: // Parser methods.
>> SubClassReference ParseSubClassReference(Record *CurRec, bool isDefm);
>> SubMultiClassReference ParseSubMultiClassReference(MultiClass *CurMC);
>>
>> - Init *ParseIDValue(Record *CurRec, IDParseMode Mode = ParseValueMode);
>> Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc,
>> IDParseMode Mode = ParseValueMode);
>> Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0,
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetTransformInfo.cpp Sun Mar 23 12:09:26 2014
>> @@ -33,21 +33,16 @@ void initializeAArch64TTIPass(PassRegist
>> namespace {
>>
>> class AArch64TTI final : public ImmutablePass, public TargetTransformInfo {
>> - const AArch64TargetMachine *TM;
>> const AArch64Subtarget *ST;
>> const AArch64TargetLowering *TLI;
>>
>> - /// Estimate the overhead of scalarizing an instruction. Insert and Extract
>> - /// are set if the result needs to be inserted and/or extracted from vectors.
>> - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
>> -
>> public:
>> - AArch64TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
>> + AArch64TTI() : ImmutablePass(ID), ST(0), TLI(0) {
>> llvm_unreachable("This pass cannot be directly constructed");
>> }
>>
>> AArch64TTI(const AArch64TargetMachine *TM)
>> - : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
>> + : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
>> TLI(TM->getTargetLowering()) {
>> initializeAArch64TTIPass(*PassRegistry::getPassRegistry());
>> }
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Sun Mar 23 12:09:26 2014
>> @@ -207,8 +207,6 @@ namespace {
>> const { return 0; }
>> unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> - unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
>> - const { return 0; }
>> unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
>> @@ -219,8 +217,6 @@ namespace {
>> const { return 0; }
>> unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> - unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
>> - const { return 0; }
>> unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
>> @@ -238,10 +234,6 @@ namespace {
>> const { return 0; }
>> unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
>> unsigned Op) const { return 0; }
>> - unsigned getSsatBitPosValue(const MachineInstr &MI,
>> - unsigned Op) const { return 0; }
>> - uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
>> - const {return 0; }
>> uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
>> const { return 0; }
>>
>> @@ -270,8 +262,6 @@ namespace {
>> return 0;
>> }
>>
>> - uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
>> - const { return 0;}
>> uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
>> const { return 0;}
>> uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
>> @@ -282,8 +272,6 @@ namespace {
>> const { return 0; }
>> uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> - uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
>> - const { return 0; }
>> uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
>> const { return 0; }
>> uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Sun Mar 23 12:09:26 2014
>> @@ -105,8 +105,6 @@ class ARMFastISel final : public FastISe
>>
>> // Code from FastISel.cpp.
>> private:
>> - unsigned FastEmitInst_(unsigned MachineInstOpcode,
>> - const TargetRegisterClass *RC);
>> unsigned FastEmitInst_r(unsigned MachineInstOpcode,
>> const TargetRegisterClass *RC,
>> unsigned Op0, bool Op0IsKill);
>> @@ -123,10 +121,6 @@ class ARMFastISel final : public FastISe
>> const TargetRegisterClass *RC,
>> unsigned Op0, bool Op0IsKill,
>> uint64_t Imm);
>> - unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
>> - const TargetRegisterClass *RC,
>> - unsigned Op0, bool Op0IsKill,
>> - const ConstantFP *FPImm);
>> unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
>> const TargetRegisterClass *RC,
>> unsigned Op0, bool Op0IsKill,
>> @@ -135,13 +129,6 @@ class ARMFastISel final : public FastISe
>> unsigned FastEmitInst_i(unsigned MachineInstOpcode,
>> const TargetRegisterClass *RC,
>> uint64_t Imm);
>> - unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
>> - const TargetRegisterClass *RC,
>> - uint64_t Imm1, uint64_t Imm2);
>> -
>> - unsigned FastEmitInst_extractsubreg(MVT RetVT,
>> - unsigned Op0, bool Op0IsKill,
>> - uint32_t Idx);
>>
>> // Backend specific FastISel code.
>> private:
>> @@ -313,16 +300,6 @@ unsigned ARMFastISel::constrainOperandRe
>> return Op;
>> }
>>
>> -unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
>> - const TargetRegisterClass* RC) {
>> - unsigned ResultReg = createResultReg(RC);
>> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
>> -
>> - AddOptionalDefs(
>> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg));
>> - return ResultReg;
>> -}
>> -
>> unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
>> const TargetRegisterClass *RC,
>> unsigned Op0, bool Op0IsKill) {
>> @@ -431,32 +408,6 @@ unsigned ARMFastISel::FastEmitInst_ri(un
>> return ResultReg;
>> }
>>
>> -unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
>> - const TargetRegisterClass *RC,
>> - unsigned Op0, bool Op0IsKill,
>> - const ConstantFP *FPImm) {
>> - unsigned ResultReg = createResultReg(RC);
>> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
>> -
>> - // Make sure the input operand is sufficiently constrained to be legal
>> - // for this instruction.
>> - Op0 = constrainOperandRegClass(II, Op0, 1);
>> - if (II.getNumDefs() >= 1) {
>> - AddOptionalDefs(
>> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
>> - .addReg(Op0, Op0IsKill * RegState::Kill)
>> - .addFPImm(FPImm));
>> - } else {
>> - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
>> - .addReg(Op0, Op0IsKill * RegState::Kill)
>> - .addFPImm(FPImm));
>> - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>> - TII.get(TargetOpcode::COPY), ResultReg)
>> - .addReg(II.ImplicitDefs[0]));
>> - }
>> - return ResultReg;
>> -}
>> -
>> unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
>> const TargetRegisterClass *RC,
>> unsigned Op0, bool Op0IsKill,
>> @@ -506,41 +457,6 @@ unsigned ARMFastISel::FastEmitInst_i(uns
>> return ResultReg;
>> }
>>
>> -unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
>> - const TargetRegisterClass *RC,
>> - uint64_t Imm1, uint64_t Imm2) {
>> - unsigned ResultReg = createResultReg(RC);
>> - const MCInstrDesc &II = TII.get(MachineInstOpcode);
>> -
>> - if (II.getNumDefs() >= 1) {
>> - AddOptionalDefs(
>> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
>> - .addImm(Imm1)
>> - .addImm(Imm2));
>> - } else {
>> - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
>> - .addImm(Imm1).addImm(Imm2));
>> - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>> - TII.get(TargetOpcode::COPY),
>> - ResultReg)
>> - .addReg(II.ImplicitDefs[0]));
>> - }
>> - return ResultReg;
>> -}
>> -
>> -unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
>> - unsigned Op0, bool Op0IsKill,
>> - uint32_t Idx) {
>> - unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
>> - assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
>> - "Cannot yet extract from physregs");
>> -
>> - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
>> - DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
>> - .addReg(Op0, getKillRegState(Op0IsKill), Idx));
>> - return ResultReg;
>> -}
>> -
>> // TODO: Don't worry about 64-bit now, but when this is fixed remove the
>> // checks from the various callers.
>> unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Sun Mar 23 12:09:26 2014
>> @@ -117,9 +117,6 @@ private:
>> unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
>> unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
>>
>> - void emitGlobalAddressUnaligned(const GlobalValue *GV, unsigned Reloc,
>> - int Offset) const;
>> -
>> /// Expand pseudo instructions with accumulator register operands.
>> void expandACCInstr(MachineBasicBlock::instr_iterator MI,
>> MachineBasicBlock &MBB, unsigned Opc) const;
>> @@ -280,14 +277,6 @@ void MipsCodeEmitter::emitGlobalAddress(
>> MayNeedFarStub));
>> }
>>
>> -void MipsCodeEmitter::emitGlobalAddressUnaligned(const GlobalValue *GV,
>> - unsigned Reloc, int Offset) const {
>> - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
>> - const_cast<GlobalValue *>(GV), 0, false));
>> - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset() + Offset,
>> - Reloc, const_cast<GlobalValue *>(GV), 0, false));
>> -}
>> -
>> void MipsCodeEmitter::
>> emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
>> MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
>>
>> Modified: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp Sun Mar 23 12:09:26 2014
>> @@ -384,16 +384,12 @@ namespace {
>> unsigned getOffsetOf(MachineInstr *MI) const;
>> unsigned getUserOffset(CPUser&) const;
>> void dumpBBs();
>> - void verify();
>>
>> bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
>> unsigned Disp, bool NegativeOK);
>> bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
>> const CPUser &U);
>>
>> - bool isLongFormOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
>> - const CPUser &U);
>> -
>> void computeBlockSize(MachineBasicBlock *MBB);
>> MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
>> void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
>> @@ -427,14 +423,6 @@ namespace {
>> char MipsConstantIslands::ID = 0;
>> } // end of anonymous namespace
>>
>> -
>> -bool MipsConstantIslands::isLongFormOffsetInRange
>> - (unsigned UserOffset, unsigned TrialOffset,
>> - const CPUser &U) {
>> - return isOffsetInRange(UserOffset, TrialOffset,
>> - U.getLongFormMaxDisp(), U.NegOk);
>> -}
>> -
>> bool MipsConstantIslands::isOffsetInRange
>> (unsigned UserOffset, unsigned TrialOffset,
>> const CPUser &U) {
>>
>> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Sun Mar 23 12:09:26 2014
>> @@ -2440,24 +2440,3 @@ bool NVPTXDAGToDAGISel::SelectInlineAsmM
>> }
>> return true;
>> }
>> -
>> -// Return true if N is a undef or a constant.
>> -// If N was undef, return a (i8imm 0) in Retval
>> -// If N was imm, convert it to i8imm and return in Retval
>> -// Note: The convert to i8imm is required, otherwise the
>> -// pattern matcher inserts a bunch of IMOVi8rr to convert
>> -// the imm to i8imm, and this causes instruction selection
>> -// to fail.
>> -bool NVPTXDAGToDAGISel::UndefOrImm(SDValue Op, SDValue N, SDValue &Retval) {
>> - if (!(N.getOpcode() == ISD::UNDEF) && !(N.getOpcode() == ISD::Constant))
>> - return false;
>> -
>> - if (N.getOpcode() == ISD::UNDEF)
>> - Retval = CurDAG->getTargetConstant(0, MVT::i8);
>> - else {
>> - ConstantSDNode *cn = cast<ConstantSDNode>(N.getNode());
>> - unsigned retval = cn->getZExtValue();
>> - Retval = CurDAG->getTargetConstant(retval, MVT::i8);
>> - }
>> - return true;
>> -}
>>
>> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (original)
>> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h Sun Mar 23 12:09:26 2014
>> @@ -91,7 +91,5 @@ private:
>>
>> bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
>>
>> - bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
>> -
>> };
>> }
>>
>> Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
>> +++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Sun Mar 23 12:09:26 2014
>> @@ -127,7 +127,6 @@ class PPCFastISel final : public FastISe
>> bool SelectStore(const Instruction *I);
>> bool SelectBranch(const Instruction *I);
>> bool SelectIndirectBr(const Instruction *I);
>> - bool SelectCmp(const Instruction *I);
>> bool SelectFPExt(const Instruction *I);
>> bool SelectFPTrunc(const Instruction *I);
>> bool SelectIToFP(const Instruction *I, bool IsSigned);
>>
>> Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Sun Mar 23 12:09:26 2014
>> @@ -326,9 +326,7 @@ struct AddressSanitizer : public Functio
>> private:
>> void initializeCallbacks(Module &M);
>>
>> - bool ShouldInstrumentGlobal(GlobalVariable *G);
>> bool LooksLikeCodeInBug11395(Instruction *I);
>> - void FindDynamicInitializers(Module &M);
>> bool GlobalIsLinkerInitialized(GlobalVariable *G);
>> bool InjectCoverage(Function &F, const ArrayRef<BasicBlock*> AllBlocks);
>> void InjectCoverageAtBlock(Function &F, BasicBlock &BB);
>>
>> Modified: llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Instrumentation/BoundsChecking.cpp Sun Mar 23 12:09:26 2014
>> @@ -62,8 +62,6 @@ namespace {
>>
>> BasicBlock *getTrapBB();
>> void emitBranchToTrap(Value *Cmp = 0);
>> - bool computeAllocSize(Value *Ptr, APInt &Offset, Value* &OffsetValue,
>> - APInt &Size, Value* &SizeValue);
>> bool instrument(Value *Ptr, Value *Val);
>> };
>> }
>>
>> Modified: llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp Sun Mar 23 12:09:26 2014
>> @@ -501,7 +501,6 @@ struct MemorySanitizerVisitor : public I
>> Instruction *OrigIns;
>> ShadowOriginAndInsertPoint(Value *S, Value *O, Instruction *I)
>> : Shadow(S), Origin(O), OrigIns(I) { }
>> - ShadowOriginAndInsertPoint() : Shadow(0), Origin(0), OrigIns(0) { }
>> };
>> SmallVector<ShadowOriginAndInsertPoint, 16> InstrumentationList;
>> SmallVector<Instruction*, 16> StoreList;
>>
>> Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Sun Mar 23 12:09:26 2014
>> @@ -79,9 +79,6 @@ namespace {
>> return dyn_cast<BranchInst>(BB->getTerminator());
>> }
>>
>> - /// Return the condition of the branch terminating the given basic block.
>> - static Value *getBrCondtion(BasicBlock *);
>> -
>> /// Derive the precondition block (i.e the block that guards the loop
>> /// preheader) from the given preheader.
>> static BasicBlock *getPrecondBb(BasicBlock *PreHead);
>> @@ -292,11 +289,6 @@ bool LIRUtil::isAlmostEmpty(BasicBlock *
>> return false;
>> }
>>
>> -Value *LIRUtil::getBrCondtion(BasicBlock *BB) {
>> - BranchInst *Br = getBranch(BB);
>> - return Br ? Br->getCondition() : 0;
>> -}
>> -
>> BasicBlock *LIRUtil::getPrecondBb(BasicBlock *PreHead) {
>> if (BasicBlock *BB = PreHead->getSinglePredecessor()) {
>> BranchInst *Br = getBranch(BB);
>>
>> Modified: llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SCCP.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Transforms/Scalar/SCCP.cpp (original)
>> +++ llvm/trunk/lib/Transforms/Scalar/SCCP.cpp Sun Mar 23 12:09:26 2014
>> @@ -491,7 +491,6 @@ private:
>> }
>> void visitCallSite (CallSite CS);
>> void visitResumeInst (TerminatorInst &I) { /*returns void*/ }
>> - void visitUnwindInst (TerminatorInst &I) { /*returns void*/ }
>> void visitUnreachableInst(TerminatorInst &I) { /*returns void*/ }
>> void visitFenceInst (FenceInst &I) { /*returns void*/ }
>> void visitAtomicCmpXchgInst (AtomicCmpXchgInst &I) { markOverdefined(&I); }
>>
>> Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=204560&r1=204559&r2=204560&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
>> +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Sun Mar 23 12:09:26 2014
>> @@ -41,8 +41,6 @@ public:
>>
>> void run(raw_ostream &o);
>> private:
>> - void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
>> - void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
>> int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
>> std::string getInstructionCase(Record *R, CodeGenTarget &Target);
>> void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
>>
>>
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