[PATCH][Mips] Add cpu octeon and some instructions

[Daniel Sanders]

Thanks. LGTM.

> I am a bit unsure about the naming of the register classes. I used OCTEON_ as
> prefix. Maybe there are better names...

I'm happy with 'OCTEON_'. It's possible that 'cnMIPS_' might be a better prefix but I'm only guessing that they are added by cnMIPS. The documentation for cnMIPS talks about them as if they already existed.

> -----Original Message-----
> From: Kai Nacke [mailto:kai.nacke at redstar.de]
> Sent: 19 March 2014 17:30
> To: Daniel Sanders; llvm-commits
> Subject: Re: [PATCH][Mips] Add cpu octeon and some instructions
> 
> Hi Daniel,
> 
> I addressed all your comments.
> I am a bit unsure about the naming of the register classes. I used OCTEON_ as
> prefix. Maybe there are better names...
> 
> Regards,
> Kai
> 
> On 18.03.2014 17:10, Daniel Sanders wrote:
> > Hi,
> >
> > Thanks for the patch. I've got a couple minor suggestions
> >
> > I see that the commented out P[0-2] registers on the Defs on the DMUL
> instruction are cnMIPS specific. Could you define them in
> MipsRegisterInfo.td and uncomment the defs? They should probably be
> marked unallocatable for now.
> >
> > In lib/Target/Mips/MipsISelLowering.cpp, there is an else that should be on
> the same line as the closing brace.
> >
> > Could you add the registers to the 'OCTEON:' lines of the CodeGen tests? It
> should be safe to hardcode them since they will be the argument/return
> registers for the N64 ABI.
> >
> > Other than those, the patch LGTM.
> >
> >> -----Original Message-----
> >> From: Kai Nacke [mailto:kai.nacke at redstar.de]
> >> Sent: 16 March 2014 22:26
> >> To: llvm-commits; Daniel Sanders
> >> Subject: [PATCH][Mips] Add cpu octeon and some instructions
> >>
> >> Hi all!
> >>
> >> The Octeon cpu from Cavium Networks is mips64r2 based and has an
> >> extended instruction set. In order to utilize this with LLVM, a new
> >> cpu feature "octeon" and a subtarget feature "cnmips" is added. A
> >> small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also
> added.
> >> LLVM generates dmul, pop and dpop instructions with option
> >> -mcpu=octeon or -mattr=+cnmips.
> >>
> >> Please review.
> >>
> >> Regards,
> >> Kai