[llvm] r204270 - R600/SI: Don't display the GDS bit.

Matt Arsenault Matthew.Arsenault at amd.com
Wed Mar 19 15:19:43 PDT 2014 

Author: arsenm
Date: Wed Mar 19 17:19:43 2014
New Revision: 204270

URL: http://llvm.org/viewvc/llvm-project?rev=204270&view=rev
Log:
R600/SI: Don't display the GDS bit.

It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.td
    llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll
    llvm/trunk/test/CodeGen/R600/atomic_load_add.ll
    llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll
    llvm/trunk/test/CodeGen/R600/local-memory-two-objects.ll
    llvm/trunk/test/CodeGen/R600/local-memory.ll

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Wed Mar 19 17:19:43 2014
@@ -395,7 +395,7 @@ class DS_Load_Helper <bits<8> op, string
   op,
   (outs regClass:$vdst),
   (ins i1imm:$gds, VReg_32:$addr, i16imm:$offset),
-  asm#" $gds, $vdst, $addr, $offset, [M0]",
+  asm#" $vdst, $addr, $offset, [M0]",
   []> {
   let data0 = 0;
   let data1 = 0;
@@ -407,7 +407,7 @@ class DS_Store_Helper <bits<8> op, strin
   op,
   (outs),
   (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
-  asm#" $gds, $addr, $data0, $offset [M0]",
+  asm#" $addr, $data0, $offset [M0]",
   []> {
   let data1 = 0;
   let mayStore = 1;
@@ -419,7 +419,7 @@ class DS_1A1D_RET <bits<8> op, string as
   op,
   (outs rc:$vdst),
   (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
-  asm#" $gds, $vdst, $addr, $data0, $offset, [M0]",
+  asm#" $vdst, $addr, $data0, $offset, [M0]",
   []> {
 
   let data1 = 0;

Modified: llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/32-bit-local-address-space.ll Wed Mar 19 17:19:43 2014
@@ -69,7 +69,7 @@ define void @mul_32bit_ptr(float addrspa
 
 ; CHECK-LABEL: @infer_ptr_alignment_global_offset:
 ; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0
-; CHECK: DS_READ_B32 v{{[0-9]+}}, 0, [[REG]]
+; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]]
 define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
   %val = load float addrspace(3)* @g_lds
   store float %val, float addrspace(1)* %out

Modified: llvm/trunk/test/CodeGen/R600/atomic_load_add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/atomic_load_add.ll?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/atomic_load_add.ll (original)
+++ llvm/trunk/test/CodeGen/R600/atomic_load_add.ll Wed Mar 19 17:19:43 2014
@@ -4,7 +4,7 @@
 ; R600-CHECK-LABEL: @atomic_add_local
 ; R600-CHECK: LDS_ADD *
 ; SI-CHECK-LABEL: @atomic_add_local
-; SI-CHECK: DS_ADD_U32_RTN 0
+; SI-CHECK: DS_ADD_U32_RTN
 define void @atomic_add_local(i32 addrspace(3)* %local) {
 entry:
    %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
@@ -14,7 +14,7 @@ entry:
 ; R600-CHECK-LABEL: @atomic_add_ret_local
 ; R600-CHECK: LDS_ADD_RET *
 ; SI-CHECK-LABEL: @atomic_add_ret_local
-; SI-CHECK: DS_ADD_U32_RTN 0
+; SI-CHECK: DS_ADD_U32_RTN
 define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
 entry:
   %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst

Modified: llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll (original)
+++ llvm/trunk/test/CodeGen/R600/atomic_load_sub.ll Wed Mar 19 17:19:43 2014
@@ -4,7 +4,7 @@
 ; R600-CHECK-LABEL: @atomic_sub_local
 ; R600-CHECK: LDS_SUB *
 ; SI-CHECK-LABEL: @atomic_sub_local
-; SI-CHECK: DS_SUB_U32_RTN 0
+; SI-CHECK: DS_SUB_U32_RTN
 define void @atomic_sub_local(i32 addrspace(3)* %local) {
 entry:
    %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
@@ -14,7 +14,7 @@ entry:
 ; R600-CHECK-LABEL: @atomic_sub_ret_local
 ; R600-CHECK: LDS_SUB_RET *
 ; SI-CHECK-LABEL: @atomic_sub_ret_local
-; SI-CHECK: DS_SUB_U32_RTN 0
+; SI-CHECK: DS_SUB_U32_RTN
 define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
 entry:
   %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst

Modified: llvm/trunk/test/CodeGen/R600/local-memory-two-objects.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/local-memory-two-objects.ll?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/local-memory-two-objects.ll (original)
+++ llvm/trunk/test/CodeGen/R600/local-memory-two-objects.ll Wed Mar 19 17:19:43 2014
@@ -17,8 +17,8 @@
 ; this consistently on evergreen GPUs.
 ; EG-CHECK: LDS_WRITE
 ; EG-CHECK: LDS_WRITE
-; SI-CHECK: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
-; SI-CHECK-NOT: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW]]
+; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
+; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]]
 
 ; GROUP_BARRIER must be the last instruction in a clause
 ; EG-CHECK: GROUP_BARRIER
@@ -27,8 +27,8 @@
 ; Make sure the lds reads are using different addresses.
 ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
 ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
-; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR:v[0-9]+]]
-; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR]]
+; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]]
+; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]]
 
 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
 entry:

Modified: llvm/trunk/test/CodeGen/R600/local-memory.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/local-memory.ll?rev=204270&r1=204269&r2=204270&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/local-memory.ll (original)
+++ llvm/trunk/test/CodeGen/R600/local-memory.ll Wed Mar 19 17:19:43 2014
@@ -18,7 +18,7 @@
 
 ; EG-CHECK: LDS_WRITE
 ; SI-CHECK-NOT: S_WQM_B64
-; SI-CHECK: DS_WRITE_B32 0
+; SI-CHECK: DS_WRITE_B32
 
 ; GROUP_BARRIER must be the last instruction in a clause
 ; EG-CHECK: GROUP_BARRIER
@@ -26,7 +26,7 @@
 ; SI-CHECK: S_BARRIER
 
 ; EG-CHECK: LDS_READ_RET
-; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0
+; SI-CHECK: DS_READ_B32 {{v[0-9]+}},
 
 define void @local_memory(i32 addrspace(1)* %out) {
 entry:

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