[PATCH] R600: Implement isNarrowingProfitable.

[Matt Arsenault]

http://llvm-reviews.chandlerc.com/D3113

Files:
  lib/Target/R600/AMDGPUISelLowering.cpp
  lib/Target/R600/AMDGPUISelLowering.h

Index: lib/Target/R600/AMDGPUISelLowering.cpp
===================================================================
--- lib/Target/R600/AMDGPUISelLowering.cpp
+++ lib/Target/R600/AMDGPUISelLowering.cpp
@@ -328,6 +328,10 @@
          (Dest->getPrimitiveSizeInBits() % 32 == 0);
 }
 
+bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
+  return SrcVT.getScalarSizeInBits() > 32 || DestVT.getScalarSizeInBits() <= 32;
+}
+
 //===---------------------------------------------------------------------===//
 // TargetLowering Callbacks
 //===---------------------------------------------------------------------===//
Index: lib/Target/R600/AMDGPUISelLowering.h
===================================================================
--- lib/Target/R600/AMDGPUISelLowering.h
+++ lib/Target/R600/AMDGPUISelLowering.h
@@ -108,6 +108,8 @@
   virtual bool isFNegFree(EVT VT) const override;
   virtual bool isTruncateFree(EVT Src, EVT Dest) const override;
   virtual bool isTruncateFree(Type *Src, Type *Dest) const override;
+  virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
+
   virtual MVT getVectorIdxTy() const override;
   virtual bool isLoadBitCastBeneficial(EVT, EVT) const override;
   virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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