[llvm] r204163 - Add support for scalarizing/splitting vector bswap.

[Raul E. Silvera]

Author: rsilvera
Date: Tue Mar 18 12:49:12 2014
New Revision: 204163

URL: http://llvm.org/viewvc/llvm-project?rev=204163&view=rev
Log:
Add support for scalarizing/splitting vector bswap.

Summary:
  SLP Vectorization of intrinsics (r203707) has exposed cases where the
  expansion of vector bswap is failing (PR19151).

Reviewers: hfinkel

CC: chandlerc

Differential Revision: http://llvm-reviews.chandlerc.com/D3104

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/test/CodeGen/Mips/bswap.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=204163&r1=204162&r2=204163&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Mar 18 12:49:12 2014
@@ -65,6 +65,7 @@ void DAGTypeLegalizer::ScalarizeVectorRe
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::ANY_EXTEND:
+  case ISD::BSWAP:
   case ISD::CTLZ:
   case ISD::CTPOP:
   case ISD::CTTZ:
@@ -533,6 +534,7 @@ void DAGTypeLegalizer::SplitVectorResult
     SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
     break;
 
+  case ISD::BSWAP:
   case ISD::CONVERT_RNDSAT:
   case ISD::CTLZ:
   case ISD::CTTZ:

Modified: llvm/trunk/test/CodeGen/Mips/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/bswap.ll?rev=204163&r1=204162&r2=204163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/bswap.ll Tue Mar 18 12:49:12 2014
@@ -22,7 +22,26 @@ entry:
   ret i64 %or.7
 }
 
+define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
+entry:
+; MIPS32-LABEL: bswapv4i32:
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; mips16: .ent bswapv4i32
+  %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)
+  ret <4 x i32> %ret
+}
+
+
+
 declare i32 @llvm.bswap.i32(i32) nounwind readnone
 
 declare i64 @llvm.bswap.i64(i64) nounwind readnone
 
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone