[PATCH] Add support for scalarizing/splitting vector bswap.
Raul Silvera
rsilvera at google.com
Tue Mar 18 10:34:56 PDT 2014
rsilvera added you to the CC list for the revision "Add support for scalarizing/splitting vector bswap.".
Hi chandlerc, hfinkel,
SLP Vectorization of intrinsics (r203707) has exposed cases where the
expansion of vector bswap is failing (PR19151).
http://llvm-reviews.chandlerc.com/D3104
BRANCH
master
ARCANIST PROJECT
llvm
Files:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
test/CodeGen/Mips/bswap.ll
Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -65,6 +65,7 @@
case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
case ISD::ANY_EXTEND:
+ case ISD::BSWAP:
case ISD::CTLZ:
case ISD::CTPOP:
case ISD::CTTZ:
@@ -533,6 +534,7 @@
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
break;
+ case ISD::BSWAP:
case ISD::CONVERT_RNDSAT:
case ISD::CTLZ:
case ISD::CTTZ:
Index: test/CodeGen/Mips/bswap.ll
===================================================================
--- test/CodeGen/Mips/bswap.ll
+++ test/CodeGen/Mips/bswap.ll
@@ -22,7 +22,26 @@
ret i64 %or.7
}
+define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
+entry:
+; MIPS32-LABEL: bswapv4i32:
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MIPS32: wsbh $[[R0:[0-9]+]]
+; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; mips16: .ent bswapv4i32
+ %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)
+ ret <4 x i32> %ret
+}
+
+
+
declare i32 @llvm.bswap.i32(i32) nounwind readnone
declare i64 @llvm.bswap.i64(i64) nounwind readnone
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
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