[llvm] r203767 - [TableGen] Optionally forbid overlap between named and positional operands
Jim Grosbach
grosbach at apple.com
Thu Mar 13 15:39:48 PDT 2014
Fantastic. Thank you!
-jim
On Mar 13, 2014, at 12:57 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> Author: hfinkel
> Date: Thu Mar 13 02:57:54 2014
> New Revision: 203767
>
> URL: http://llvm.org/viewvc/llvm-project?rev=203767&view=rev
> Log:
> [TableGen] Optionally forbid overlap between named and positional operands
>
> There are currently two schemes for mapping instruction operands to
> instruction-format variables for generating the instruction encoders and
> decoders for the assembler and disassembler respectively: a) to map by name and
> b) to map by position.
>
> In the long run, we'd like to remove the position-based scheme and use only
> name-based mapping. Unfortunately, the name-based scheme currently cannot deal
> with complex operands (those with suboperands), and so we currently must use
> the position-based scheme for those. On the other hand, the position-based
> scheme cannot deal with (register) variables that are split into multiple
> ranges. An upcoming commit to the PowerPC backend (adding VSX support) will
> require this capability. While we could teach the position-based scheme to
> handle that, since we'd like to move away from the position-based mapping
> generally, it seems silly to teach it new tricks now. What makes more sense is
> to allow for partial transitioning: use the name-based mapping when possible,
> and only use the position-based scheme when necessary.
>
> Now the problem is that mixing the two sensibly was not possible: the
> position-based mapping would map based on position, but would not skip those
> variables that were mapped by name. Instead, the two sets of assignments would
> overlap. However, I cannot currently change the current behavior, because there
> are some backends that rely on it [I think mistakenly, but I'll send a message
> to llvmdev about that]. So I've added a new TableGen bit variable:
> noNamedPositionallyEncodedOperands, that can be used to cause the
> position-based mapping to skip variables mapped by name.
>
> Modified:
> llvm/trunk/include/llvm/Target/Target.td
> llvm/trunk/lib/Target/PowerPC/PPC.td
> llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=203767&r1=203766&r2=203767&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/Target.td (original)
> +++ llvm/trunk/include/llvm/Target/Target.td Thu Mar 13 02:57:54 2014
> @@ -697,6 +697,15 @@ class InstrInfo {
> // generator has better support for complex operands and targets have
> // migrated away from using positionally encoded operands.
> bit decodePositionallyEncodedOperands = 0;
> +
> + // When set, this indicates that there will be no overlap between those
> + // operands that are matched by ordering (positional operands) and those
> + // matched by name.
> + //
> + // This option is temporary; it will go away once the TableGen decoder
> + // generator has better support for complex operands and targets have
> + // migrated away from using positionally encoded operands.
> + bit noNamedPositionallyEncodedOperands = 0;
> }
>
> // Standard Pseudo Instructions.
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPC.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.td?rev=203767&r1=203766&r2=203767&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPC.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPC.td Thu Mar 13 02:57:54 2014
> @@ -288,6 +288,8 @@ def PPCInstrInfo : InstrInfo {
>
> // FIXME: Unset this when no longer needed!
> let decodePositionallyEncodedOperands = 1;
> +
> + let noNamedPositionallyEncodedOperands = 1;
> }
>
> def PPCAsmParser : AsmParser {
>
> Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=203767&r1=203766&r2=203767&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Thu Mar 13 02:57:54 2014
> @@ -48,6 +48,7 @@ private:
> void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
> const std::string &VarName,
> unsigned &NumberedOp,
> + std::set<unsigned> &NamedOpIndices,
> std::string &Case, CodeGenTarget &Target);
>
> };
> @@ -71,6 +72,7 @@ int CodeEmitterGen::getVariableBit(const
> void CodeEmitterGen::
> AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
> unsigned &NumberedOp,
> + std::set<unsigned> &NamedOpIndices,
> std::string &Case, CodeGenTarget &Target) {
> CodeGenInstruction &CGI = Target.getInstruction(R);
>
> @@ -103,7 +105,9 @@ AddCodeToMergeInOperand(Record *R, BitsI
> /// If this operand is not supposed to be emitted by the
> /// generated emitter, skip it.
> while (NumberedOp < NumberOps &&
> - CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
> + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
> + (NamedOpIndices.size() && NamedOpIndices.count(
> + CGI.Operands.getSubOperandNumber(NumberedOp).first))))
> ++NumberedOp;
>
> OpIdx = NumberedOp++;
> @@ -180,6 +184,21 @@ std::string CodeEmitterGen::getInstructi
> const std::vector<RecordVal> &Vals = R->getValues();
> unsigned NumberedOp = 0;
>
> + std::set<unsigned> NamedOpIndices;
> + // Collect the set of operand indices that might correspond to named
> + // operand, and skip these when assigning operands based on position.
> + if (Target.getInstructionSet()->
> + getValueAsBit("noNamedPositionallyEncodedOperands")) {
> + CodeGenInstruction &CGI = Target.getInstruction(R);
> + for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
> + unsigned OpIdx;
> + if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
> + continue;
> +
> + NamedOpIndices.insert(OpIdx);
> + }
> + }
> +
> // Loop over all of the fields in the instruction, determining which are the
> // operands to the instruction.
> for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
> @@ -188,7 +207,8 @@ std::string CodeEmitterGen::getInstructi
> if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
> continue;
>
> - AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
> + AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp,
> + NamedOpIndices, Case, Target);
> }
>
> std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
>
> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=203767&r1=203766&r2=203767&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Mar 13 02:57:54 2014
> @@ -1754,6 +1754,19 @@ static bool populateInstruction(CodeGenT
> const std::vector<RecordVal> &Vals = Def.getValues();
> unsigned NumberedOp = 0;
>
> + std::set<unsigned> NamedOpIndices;
> + if (Target.getInstructionSet()->
> + getValueAsBit("noNamedPositionallyEncodedOperands"))
> + // Collect the set of operand indices that might correspond to named
> + // operand, and skip these when assigning operands based on position.
> + for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
> + unsigned OpIdx;
> + if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx))
> + continue;
> +
> + NamedOpIndices.insert(OpIdx);
> + }
> +
> for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
> // Ignore fixed fields in the record, we're looking for values like:
> // bits<5> RST = { ?, ?, ?, ?, ? };
> @@ -1803,7 +1816,9 @@ static bool populateInstruction(CodeGenT
>
> unsigned NumberOps = CGI.Operands.size();
> while (NumberedOp < NumberOps &&
> - CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
> + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
> + (NamedOpIndices.size() && NamedOpIndices.count(
> + CGI.Operands.getSubOperandNumber(NumberedOp).first))))
> ++NumberedOp;
>
> OpIdx = NumberedOp++;
>
>
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