[llvm] r203762 - ARM: support emission of complex SO expressions

[Saleem Abdulrasool]

Author: compnerd
Date: Thu Mar 13 02:02:41 2014
New Revision: 203762

URL: http://llvm.org/viewvc/llvm-project?rev=203762&view=rev
Log:
ARM: support emission of complex SO expressions

Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

Added:
    llvm/trunk/test/MC/ARM/shift-offset-addressing-emission.s
Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=203762&r1=203761&r2=203762&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Thu Mar 13 02:02:41 2014
@@ -271,8 +271,19 @@ public:
   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
-    unsigned SoImm = MI.getOperand(Op).getImm();
-    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
+    int SoImmVal = -1;
+
+    const MCOperand &MO = MI.getOperand(Op);
+    if (MO.isImm()) {
+      SoImmVal = ARM_AM::getSOImmVal(MO.getImm());
+    } else if (MO.isExpr()) {
+      int64_t Value;
+      bool Invalid = MO.getExpr()->EvaluateAsAbsolute(Value);
+      assert(!Invalid && "non-constant expression is not a valid SOImm operand");
+      assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
+             "expression must be representable in 32 bits");
+      SoImmVal = Value;
+    }
     assert(SoImmVal != -1 && "Not a valid so_imm value!");
 
     // Encode rotate_imm.

Added: llvm/trunk/test/MC/ARM/shift-offset-addressing-emission.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/shift-offset-addressing-emission.s?rev=203762&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/shift-offset-addressing-emission.s (added)
+++ llvm/trunk/test/MC/ARM/shift-offset-addressing-emission.s Thu Mar 13 02:02:41 2014
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s \
+@ RUN:   | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s
+
+	cmp r0, #(.L2 - .L1)
+.L1:
+.L2:
+
+@ CHECK: 0:	cmp	r0, #0
+