[llvm] r203718 - [X86] Add peephole for masked rotate amount

[Adam Nemet]

Author: anemet
Date: Wed Mar 12 16:20:55 2014
New Revision: 203718

URL: http://llvm.org/viewvc/llvm-project?rev=203718&view=rev
Log:
[X86] Add peephole for masked rotate amount

Extend what's currently done for shift because the HW performs this masking
implicitly:

   (rotl:i32 x, (and y, 31)) -> (rotl:i32 x, y)

I use the newly factored out multiclass that was only supporting shifts so
far.

For testing I extended my testcase for the new rotation idiom.

<rdar://problem/15295856>

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/test/CodeGen/X86/rotate4.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=203718&r1=203717&r2=203718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Mar 12 16:20:55 2014
@@ -1556,6 +1556,8 @@ multiclass MaskedShiftAmountPats<SDNode
 defm : MaskedShiftAmountPats<shl, "SHL">;
 defm : MaskedShiftAmountPats<srl, "SHR">;
 defm : MaskedShiftAmountPats<sra, "SAR">;
+defm : MaskedShiftAmountPats<rotl, "ROL">;
+defm : MaskedShiftAmountPats<rotr, "ROR">;
 
 // (anyext (setcc_carry)) -> (setcc_carry)
 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),

Modified: llvm/trunk/test/CodeGen/X86/rotate4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rotate4.ll?rev=203718&r1=203717&r2=203718&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rotate4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rotate4.ll Wed Mar 12 16:20:55 2014
@@ -5,6 +5,7 @@
 
 define i32 @rotate_left_32(i32 %a, i32 %b) {
 ; CHECK-LABEL: rotate_left_32:
+; CHECK-NOT: and
 ; CHECK: roll
 entry:
   %and = and i32 %b, 31
@@ -18,6 +19,7 @@ entry:
 
 define i32 @rotate_right_32(i32 %a, i32 %b) {
 ; CHECK-LABEL: rotate_right_32:
+; CHECK-NOT: and
 ; CHECK: rorl
 entry:
   %and = and i32 %b, 31
@@ -31,6 +33,7 @@ entry:
 
 define i64 @rotate_left_64(i64 %a, i64 %b) {
 ; CHECK-LABEL: rotate_left_64:
+; CHECK-NOT: and
 ; CHECK: rolq
 entry:
   %and = and i64 %b, 63
@@ -44,6 +47,7 @@ entry:
 
 define i64 @rotate_right_64(i64 %a, i64 %b) {
 ; CHECK-LABEL: rotate_right_64:
+; CHECK-NOT: and
 ; CHECK: rorq
 entry:
   %and = and i64 %b, 63
@@ -59,6 +63,7 @@ entry:
 
 define void @rotate_left_m32(i32 *%pa, i32 %b) {
 ; CHECK-LABEL: rotate_left_m32:
+; CHECK-NOT: and
 ; CHECK: roll
 ; no store:
 ; CHECK-NOT: mov
@@ -76,6 +81,7 @@ entry:
 
 define void @rotate_right_m32(i32 *%pa, i32 %b) {
 ; CHECK-LABEL: rotate_right_m32:
+; CHECK-NOT: and
 ; CHECK: rorl
 ; no store:
 ; CHECK-NOT: mov
@@ -93,6 +99,7 @@ entry:
 
 define void @rotate_left_m64(i64 *%pa, i64 %b) {
 ; CHECK-LABEL: rotate_left_m64:
+; CHECK-NOT: and
 ; CHECK: rolq
 ; no store:
 ; CHECK-NOT: mov
@@ -110,6 +117,7 @@ entry:
 
 define void @rotate_right_m64(i64 *%pa, i64 %b) {
 ; CHECK-LABEL: rotate_right_m64:
+; CHECK-NOT: and
 ; CHECK: rorq
 ; no store:
 ; CHECK-NOT: mov