[PATCH] Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)

[Craig Topper]

Is there an earlier check to ensure SSE2 is supported? Just want to make
sure we have everything covered.


On Mon, Mar 10, 2014 at 6:15 PM, Hans Wennborg <hans at chromium.org> wrote:

>   Actually uploading the new patch...
>
> Hi craig.topper,
>
> http://llvm-reviews.chandlerc.com/D3009
>
> CHANGE SINCE LAST DIFF
>   http://llvm-reviews.chandlerc.com/D3009?vs=7725&id=7728#toc
>
> Files:
>   lib/Target/X86/X86ISelLowering.cpp
>   test/CodeGen/X86/isint.ll
>
> Index: lib/Target/X86/X86ISelLowering.cpp
> ===================================================================
> --- lib/Target/X86/X86ISelLowering.cpp
> +++ lib/Target/X86/X86ISelLowering.cpp
> @@ -18056,9 +18056,25 @@
>            SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
>                                                CMP00.getValueType(),
> CMP00, CMP01,
>                                                DAG.getConstant(x86cc,
> MVT::i8));
> -          MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
> -          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
> -                                              OnesOrZeroesF);
> +
> +          MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
> +
> +          if (is64BitFP && !Subtarget->is64Bit()) {
> +            // On a 32-bit target, we cannot bitcast the 64-bit float to a
> +            // 64-bit integer, since that's not a legal type. Since
> +            // OnesOrZeroesF is all ones of all zeroes, we don't need all
> the
> +            // bits, but can do this little dance to extract the lowest
> 32 bits
> +            // and work with those going forward.
> +            SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL,
> MVT::v2f64,
> +                                           OnesOrZeroesF);
> +            SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
> +                                           Vector64);
> +            OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
> MVT::f32,
> +                                        Vector32,
> DAG.getIntPtrConstant(0));
> +            IntVT = MVT::i32;
> +          }
> +
> +          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
> OnesOrZeroesF);
>            SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
>                                        DAG.getConstant(1, IntVT));
>            SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
> ANDed);
> Index: test/CodeGen/X86/isint.ll
> ===================================================================
> --- test/CodeGen/X86/isint.ll
> +++ test/CodeGen/X86/isint.ll
> @@ -1,22 +1,46 @@
> -; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn| FileCheck %s
> +; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn |
> FileCheck %s
> +; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn |
> FileCheck %s
> +
> +; PR19059
> +; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn |
> FileCheck -check-prefix=CHECK32 %s
>
>  define i32 @isint_return(double %d) nounwind {
> +; CHECK-LABEL: isint_return:
>  ; CHECK-NOT: xor
>  ; CHECK: cvt
>    %i = fptosi double %d to i32
>  ; CHECK-NEXT: cvt
>    %e = sitofp i32 %i to double
>  ; CHECK: cmpeqsd
>    %c = fcmp oeq double %d, %e
> +; CHECK32-NOT: movd {{.*}}, %r{{.*}}
> +; CHECK32-NOT: andq
> +; CHECK-NEXT: movd
> +; CHECK-NEXT: andl
> +  %z = zext i1 %c to i32
> +  ret i32 %z
> +}
> +
> +define i32 @isint_float_return(float %f) nounwind {
> +; CHECK-LABEL: isint_float_return:
> +; CHECK-NOT: xor
> +; CHECK: cvt
> +  %i = fptosi float %f to i32
> +; CHECK-NEXT: cvt
> +  %g = sitofp i32 %i to float
> +; CHECK: cmpeqss
> +  %c = fcmp oeq float %f, %g
> +; CHECK-NOT: movd {{.*}}, %r{{.*}}
>  ; CHECK-NEXT: movd
> -; CHECK-NEXT: andq
> +; CHECK-NEXT: andl
>    %z = zext i1 %c to i32
>    ret i32 %z
>  }
>
>  declare void @foo()
>
>  define void @isint_branch(double %d) nounwind {
> +; CHECK-LABEL: isint_branch:
>  ; CHECK: cvt
>    %i = fptosi double %d to i32
>  ; CHECK-NEXT: cvt
>



-- 
~Craig
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