[PATCH] IR: add failure ordering to the cmpxchg instruction

[JF Bastien]

I don't know about the .bc file version: won't old files continue to work?
Your cmpxchg-upgrade.ll and cmpxchg-upgrade.ll.bc tests lead me to believe
that they will?

Other than this, the change looks good to me.

I assume you'll add code that recognizes the looser failure ordering and
generates better code?


On Mon, Mar 10, 2014 at 11:52 AM, Tim Northover <t.p.northover at gmail.com>wrote:

>   Thanks for taking a look. I've implemented all of those suggestions,
> which looked completely sensible.
>
>   Cheers.
>
>   Tim.
>
> http://llvm-reviews.chandlerc.com/D3023
>
> CHANGE SINCE LAST DIFF
>   http://llvm-reviews.chandlerc.com/D3023?vs=7687&id=7709#toc
>
> Files:
>   docs/LangRef.rst
>   include/llvm/CodeGen/SelectionDAG.h
>   include/llvm/CodeGen/SelectionDAGNodes.h
>   include/llvm/IR/IRBuilder.h
>   include/llvm/IR/Instructions.h
>   lib/Analysis/AliasAnalysis.cpp
>   lib/AsmParser/LLParser.cpp
>   lib/AsmParser/LLParser.h
>   lib/Bitcode/Reader/BitcodeReader.cpp
>   lib/Bitcode/Writer/BitcodeWriter.cpp
>   lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>   lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>   lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>   lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>   lib/IR/AsmWriter.cpp
>   lib/IR/AsmWriter.h
>   lib/IR/Instruction.cpp
>   lib/IR/Instructions.cpp
>   lib/IR/Verifier.cpp
>   lib/Target/ARM/ARMISelLowering.cpp
>   lib/Target/CppBackend/CPPBackend.cpp
>   lib/Target/X86/X86ISelLowering.cpp
>   lib/Transforms/IPO/MergeFunctions.cpp
>   lib/Transforms/Instrumentation/MemorySanitizer.cpp
>   lib/Transforms/Instrumentation/ThreadSanitizer.cpp
>   test/Assembler/atomic.ll
>   test/Bitcode/cmpxchg-upgrade.ll
>   test/Bitcode/cmpxchg-upgrade.ll.bc
>   test/Bitcode/memInstructions.3.2.ll
>   test/CodeGen/AArch64/atomic-ops.ll
>   test/CodeGen/ARM/atomic-64bit.ll
>   test/CodeGen/ARM/atomic-cmp.ll
>   test/CodeGen/ARM/atomic-ops-v8.ll
>   test/CodeGen/Mips/atomic.ll
>   test/CodeGen/Mips/atomicops.ll
>   test/CodeGen/PowerPC/Atomics-32.ll
>   test/CodeGen/PowerPC/Atomics-64.ll
>   test/CodeGen/PowerPC/atomic-1.ll
>   test/CodeGen/PowerPC/atomic-2.ll
>   test/CodeGen/SPARC/atomics.ll
>   test/CodeGen/SystemZ/cmpxchg-01.ll
>   test/CodeGen/SystemZ/cmpxchg-02.ll
>   test/CodeGen/SystemZ/cmpxchg-03.ll
>   test/CodeGen/SystemZ/cmpxchg-04.ll
>   test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
>   test/CodeGen/X86/Atomics-64.ll
>   test/CodeGen/X86/atomic16.ll
>   test/CodeGen/X86/atomic32.ll
>   test/CodeGen/X86/atomic64.ll
>   test/CodeGen/X86/atomic6432.ll
>   test/CodeGen/X86/atomic8.ll
>   test/CodeGen/X86/atomic_op.ll
>   test/CodeGen/X86/cmpxchg16b.ll
>   test/CodeGen/X86/coalescer-remat.ll
>   test/CodeGen/X86/nocx16.ll
>   test/Instrumentation/AddressSanitizer/test64.ll
>   test/Instrumentation/MemorySanitizer/atomics.ll
>   test/Instrumentation/ThreadSanitizer/atomic.ll
>   test/Transforms/LowerAtomic/atomic-swap.ll
>   test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
>
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