[llvm] r203424 - [Sparc] Add support for decoding 'swap' instruction.

[Venkatraman Govindaraju]

Author: venkatra
Date: Sun Mar  9 18:32:07 2014
New Revision: 203424

URL: http://llvm.org/viewvc/llvm-project?rev=203424&view=rev
Log:
[Sparc] Add support for decoding 'swap' instruction.

Modified:
    llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt

Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=203424&r1=203423&r2=203424&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Sun Mar  9 18:32:07 2014
@@ -211,6 +211,8 @@ static DecodeStatus DecodeJMPL(MCInst &I
                                const void *Decoder);
 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
                                  const void *Decoder);
+static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
+                               const void *Decoder);
 
 #include "SparcGenDisassemblerTables.inc"
 
@@ -439,6 +441,40 @@ static DecodeStatus DecodeReturn(MCInst
   if (isImm)
     MI.addOperand(MCOperand::CreateImm(simm13));
   else {
+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+    if (status != MCDisassembler::Success)
+      return status;
+  }
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
+                               const void *Decoder) {
+
+  unsigned rd = fieldFromInstruction(insn, 25, 5);
+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
+  unsigned rs2 = 0;
+  unsigned simm13 = 0;
+  if (isImm)
+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
+  else
+    rs2 = fieldFromInstruction(insn, 0, 5);
+
+  // Decode RD.
+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+  if (status != MCDisassembler::Success)
+    return status;
+
+  // Decode RS1.
+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+  if (status != MCDisassembler::Success)
+    return status;
+
+  // Decode RS1 | SIMM13.
+  if (isImm)
+    MI.addOperand(MCOperand::CreateImm(simm13));
+  else {
     status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=203424&r1=203423&r2=203424&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sun Mar  9 18:32:07 2014
@@ -1107,7 +1107,7 @@ let Predicates = [HasV9], hasSideEffects
  def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
                     "membar $simm13", []>;
 
-let Constraints = "$val = $dst" in {
+let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
   def SWAPrr : F3_1<3, 0b001111,
                  (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
                  "swap [$addr], $dst",

Modified: llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt?rev=203424&r1=203423&r2=203424&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt Sun Mar  9 18:32:07 2014
@@ -152,3 +152,12 @@
 
 # CHECK:      stx %o2, [%g1]
 0xd4 0x70 0x60 0x00
+
+# CHECK:     swap [%i0+%l6], %o2
+0xd4 0x7e 0x00 0x16
+
+# CHECK:     swap [%i0+32], %o2
+0xd4 0x7e 0x20 0x20
+
+# CHECK:     swap [%g1], %o2
+0xd4 0x78 0x60 0x00