[llvm] r202706 - This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
Vladimir Medic
Vladimir.Medic at imgtec.com
Mon Mar 3 05:12:59 PST 2014
Author: vmedic
Date: Mon Mar 3 07:12:59 2014
New Revision: 202706
URL: http://llvm.org/viewvc/llvm-project?rev=202706&view=rev
Log:
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
llvm/trunk/test/MC/Mips/mips-jump-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Mar 3 07:12:59 2014
@@ -1038,6 +1038,7 @@ def B : UncondBranch<BEQ>;
def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
+def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>;
def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Mon Mar 3 07:12:59 2014
@@ -206,6 +206,9 @@
# CHECK: jal 1328
0x0c 0x00 0x01 0x4c
+# CHECK: jalx 1328
+0x74 0x00 0x01 0x4c
+
# CHECK: jalr $7
0x00 0xe0 0xf8 0x09
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Mon Mar 3 07:12:59 2014
@@ -206,6 +206,9 @@
# CHECK: jal 1328
0x4c 0x01 0x00 0x0c
+# CHECK: jalx 1328
+0x4c 0x01 0x00 0x74
+
# CHECK: jalr $7
0x09 0xf8 0xe0 0x00
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt Mon Mar 3 07:12:59 2014
@@ -215,6 +215,9 @@
# CHECK: jal 1328
0x0c 0x00 0x01 0x4c
+# CHECK: jalx 1328
+0x74 0x00 0x01 0x4c
+
# CHECK: jalr $7
0x00 0xe0 0xf8 0x09
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt Mon Mar 3 07:12:59 2014
@@ -215,6 +215,9 @@
# CHECK: jal 1328
0x4c 0x01 0x00 0x0c
+# CHECK: jalx 1328
+0x4c 0x01 0x00 0x74
+
# CHECK: jalr $7
0x09 0xf8 0xe0 0x00
Modified: llvm/trunk/test/MC/Mips/mips-jump-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-jump-instructions.s?rev=202706&r1=202705&r2=202706&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-jump-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-jump-instructions.s Mon Mar 3 07:12:59 2014
@@ -101,12 +101,16 @@ end_of_code:
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK32:lab:
# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK32: jalx lab # encoding: [A,A,A,0b011101AA]
+# CHECK32: # fixup A - offset: 0, value: lab, kind: fixup_Mips_26
+# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: j 1328 # encoding: [0x4c,0x01,0x00,0x08]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
@@ -120,13 +124,16 @@ end_of_code:
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK64:lab:
# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
-
+# CHECK64: jalx lab # encoding: [A,A,A,0b011101AA]
+# CHECK64: # fixup A - offset: 0, value: lab, kind: fixup_Mips_26
+# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
j 1328
nop
@@ -140,9 +147,12 @@ end_of_code:
nop
jr $7
nop
+lab:
j $7
nop
jal $25
nop
jal $4,$25
nop
+ jalx lab
+ nop
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