[llvm] r202614 - [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
Venkatraman Govindaraju
venkatra at cs.wisc.edu
Sat Mar 1 20:43:46 PST 2014
Author: venkatra
Date: Sat Mar 1 22:43:45 2014
New Revision: 202614
URL: http://llvm.org/viewvc/llvm-project?rev=202614&view=rev
Log:
[Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
No functionality change.
Modified:
llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
Modified: llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td?rev=202614&r1=202613&r2=202614&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstr64Bit.td Sat Mar 1 22:43:45 2014
@@ -312,7 +312,7 @@ let Uses = [ICC], cc = 0b10 in
// Conditional moves on %xcc.
let Uses = [ICC], Constraints = "$f = $rd" in {
-let cc = 0b110 in {
+let intcc = 1, cc = 0b10 in {
def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
"mov$cond %xcc, $rs2, $rd",
@@ -325,7 +325,7 @@ def MOVXCCri : F4_2<0b101100, (outs IntR
(SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
} // cc
-let opf_cc = 0b110 in {
+let intcc = 1, opf_cc = 0b10 in {
def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
"fmovs$cond %xcc, $rs2, $rd",
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td?rev=202614&r1=202613&r2=202614&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td Sat Mar 1 22:43:45 2014
@@ -131,27 +131,27 @@ multiclass fp_cond_alias<string cond, in
// fb<cond> %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), " %fcc0, $imm"),
- (BPFCC brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt %fcc0, $imm"),
- (BPFCC brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a %fcc0, $imm"),
- (BPFCCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a,pt %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt %fcc0, $imm"),
- (BPFCCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn %fcc0, $imm"),
- (BPFCCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCNT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
// fb<cond>,a,pn %fcc0, $imm
def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn %fcc0, $imm"),
- (BPFCCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
+ (BPFCCANT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
defm : cond_mov_alias<cond, condVal, " %fcc0",
MOVFCCrr, MOVFCCri,
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td?rev=202614&r1=202613&r2=202614&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrFormats.td Sat Mar 1 22:43:45 2014
@@ -211,44 +211,46 @@ class F4_1<bits<6> op3, dag outs, dag in
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
- bits<3> cc;
+ bit intcc;
+ bits<2> cc;
bits<4> cond;
bits<5> rs2;
let Inst{4-0} = rs2;
- let Inst{11} = cc{0};
- let Inst{12} = cc{1};
+ let Inst{12-11} = cc;
let Inst{13} = 0;
let Inst{17-14} = cond;
- let Inst{18} = cc{2};
+ let Inst{18} = intcc;
}
class F4_2<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
- bits<3> cc;
+ bit intcc;
+ bits<2> cc;
bits<4> cond;
bits<11> simm11;
let Inst{10-0} = simm11;
- let Inst{11} = cc{0};
- let Inst{12} = cc{1};
+ let Inst{12-11} = cc;
let Inst{13} = 1;
let Inst{17-14} = cond;
- let Inst{18} = cc{2};
+ let Inst{18} = intcc;
}
class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
string asmstr, list<dag> pattern>
: F4<op3, outs, ins, asmstr, pattern> {
bits<4> cond;
- bits<3> opf_cc;
+ bit intcc;
+ bits<2> opf_cc;
bits<5> rs2;
let Inst{18} = 0;
let Inst{17-14} = cond;
- let Inst{13-11} = opf_cc;
+ let Inst{13} = intcc;
+ let Inst{12-11} = opf_cc;
let Inst{10-5} = opf_low;
let Inst{4-0} = rs2;
}
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=202614&r1=202613&r2=202614&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sat Mar 1 22:43:45 2014
@@ -634,14 +634,18 @@ class FPBranchSPA<dag ins, string asmstr
// Conditional branch class on %fcc0-%fcc3 with predication:
multiclass FPredBranch {
- def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond %fcc0, $imm19", []>;
- def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,a %fcc0, $imm19", []>;
- def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,pn %fcc0, $imm19", []>;
- def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
- "fb$cond,a,pn %fcc0, $imm19", []>;
+ def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond $cc, $imm19", []>;
+ def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,a $cc, $imm19", []>;
+ def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,pn $cc, $imm19", []>;
+ def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
+ FCCRegs:$cc),
+ "fb$cond,a,pn $cc, $imm19", []>;
}
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
@@ -651,11 +655,12 @@ let Uses = [FCC0] in {
[(SPbrfcc bb:$imm22, imm:$cond)]>;
def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
"fb$cond,a $imm22", []>;
-
- let Predicates = [HasV9], cc = 0b00 in
- defm BPF : FPredBranch;
}
+let Predicates = [HasV9] in
+ defm BPF : FPredBranch;
+
+
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O6],
@@ -916,7 +921,7 @@ let Uses = [O6], isCall = 1, hasDelaySlo
// V9 Conditional Moves.
let Predicates = [HasV9], Constraints = "$f = $rd" in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
- let Uses = [ICC], cc = 0b100 in {
+ let Uses = [ICC], intcc = 1, cc = 0b00 in {
def MOVICCrr
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
@@ -931,7 +936,7 @@ let Predicates = [HasV9], Constraints =
(SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
}
- let Uses = [FCC0], cc = 0b000 in {
+ let Uses = [FCC0], intcc = 0, cc = 0b00 in {
def MOVFCCrr
: F4_1<0b101100, (outs IntRegs:$rd),
(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
@@ -945,7 +950,7 @@ let Predicates = [HasV9], Constraints =
(SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
}
- let Uses = [ICC], opf_cc = 0b100 in {
+ let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
def FMOVS_ICC
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
@@ -964,7 +969,7 @@ let Predicates = [HasV9], Constraints =
Requires<[HasHardQuad]>;
}
- let Uses = [FCC0], opf_cc = 0b000 in {
+ let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
def FMOVS_FCC
: F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
@@ -1026,7 +1031,6 @@ def V9FCMPQ : F3_3c<2, 0b110101, 0b0010
"fcmpq $rd, $rs1, $rs2", []>,
Requires<[HasHardQuad]>;
-
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
let rs1 = 0 in
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