[llvm] r202598 - [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.

[Venkatraman Govindaraju]

Author: venkatra
Date: Sat Mar  1 12:54:52 2014
New Revision: 202598

URL: http://llvm.org/viewvc/llvm-project?rev=202598&view=rev
Log:
[Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.

Added:
    llvm/trunk/test/MC/Sparc/sparcv9-instructions.s
Modified:
    llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td

Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=202598&r1=202597&r2=202598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Sat Mar  1 12:54:52 2014
@@ -419,7 +419,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, uns
     return Error(ErrorLoc, "invalid operand for instruction");
   }
   case Match_MnemonicFail:
-    return Error(IDLoc, "invalid instruction");
+    return Error(IDLoc, "invalid instruction mnemonic");
   }
   return true;
 }
@@ -448,11 +448,7 @@ ParseInstruction(ParseInstructionInfo &I
                  SMLoc NameLoc,
                  SmallVectorImpl<MCParsedAsmOperand*> &Operands)
 {
-  // Check if we have valid mnemonic.
-  if (!mnemonicIsValid(Name, 0)) {
-    Parser.eatToEndOfStatement();
-    return Error(NameLoc, "Unknown instruction");
-  }
+
   // First operand in MCInst is instruction mnemonic.
   Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
 

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=202598&r1=202597&r2=202598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Sat Mar  1 12:54:52 2014
@@ -67,6 +67,9 @@ static MCRegisterInfo *createSparcMCRegi
 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
                                                    StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
+  Triple TheTriple(TT);
+  if (CPU.empty())
+    CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8";
   InitSparcMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td?rev=202598&r1=202597&r2=202598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td Sat Mar  1 12:54:52 2014
@@ -143,3 +143,9 @@ def : InstAlias<"mov $simm13, $rd", (ORr
 
 // restore -> restore %g0, %g0, %g0
 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
+
+def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
+def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
+
+def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
+def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=202598&r1=202597&r2=202598&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sat Mar  1 12:54:52 2014
@@ -29,7 +29,8 @@ def Is64Bit : Predicate<"Subtarget.is64B
 
 // HasV9 - This predicate is true when the target processor supports V9
 // instructions.  Note that the machine may be running in 32-bit mode.
-def HasV9   : Predicate<"Subtarget.isV9()">;
+def HasV9   : Predicate<"Subtarget.isV9()">,
+              AssemblerPredicate<"FeatureV9">;
 
 // HasNoV9 - This predicate is true when the target doesn't have V9
 // instructions.  Use of this is just a hack for the isel not having proper

Added: llvm/trunk/test/MC/Sparc/sparcv9-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparcv9-instructions.s?rev=202598&view=auto
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparcv9-instructions.s (added)
+++ llvm/trunk/test/MC/Sparc/sparcv9-instructions.s Sat Mar  1 12:54:52 2014
@@ -0,0 +1,23 @@
+! RUN: not llvm-mc %s -arch=sparc   -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: addc %g2, %g1, %g3
+        ! V9:      addx %g2, %g1, %g3              ! encoding: [0x86,0x40,0x80,0x01]
+        addc %g2, %g1, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: addccc %g1, %g2, %g3
+        ! V9:      addxcc %g1, %g2, %g3            ! encoding: [0x86,0xc0,0x40,0x02]
+        addccc %g1, %g2, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: subc %g2, %g1, %g3
+        ! V9:      subx %g2, %g1, %g3          ! encoding: [0x86,0x60,0x80,0x01]
+        subc %g2, %g1, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: subccc %g1, %g2, %g3
+        ! V9:      subxcc %g1, %g2, %g3         ! encoding: [0x86,0xe0,0x40,0x02]
+        subccc %g1, %g2, %g3
+