[llvm] r202577 - [Sparc] Add support for decoding call instructions in the sparc disassembler.

[Venkatraman Govindaraju]

Author: venkatra
Date: Sat Mar  1 02:30:58 2014
New Revision: 202577

URL: http://llvm.org/viewvc/llvm-project?rev=202577&view=rev
Log:
[Sparc] Add support for decoding call instructions in the sparc disassembler.

Modified:
    llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
    llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt

Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=202577&r1=202576&r2=202577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Sat Mar  1 02:30:58 2014
@@ -190,6 +190,8 @@ static DecodeStatus DecodeStoreDFP(MCIns
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
+                               uint64_t Address, const void *Decoder);
 
 #include "SparcGenDisassemblerTables.inc"
 
@@ -336,3 +338,22 @@ static DecodeStatus DecodeStoreQFP(MCIns
   return DecodeMem(Inst, insn, Address, Decoder, false,
                    DecodeQFPRegsRegisterClass);
 }
+
+static bool tryAddingSymbolicOperand(int64_t Value,  bool isBranch,
+                                     uint64_t Address, uint64_t Offset,
+                                     uint64_t Width, MCInst &MI,
+                                     const void *Decoder) {
+  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
+  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
+                                       Offset, Width);
+}
+
+static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
+                               uint64_t Address, const void *Decoder) {
+  unsigned tgt = fieldFromInstruction(insn, 0, 30);
+  tgt <<= 2;
+  if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
+                                0, 30, MI, Decoder))
+    MI.addOperand(MCOperand::CreateImm(tgt));
+  return MCDisassembler::Success;
+}

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=202577&r1=202576&r2=202577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sat Mar  1 02:30:58 2014
@@ -106,6 +106,7 @@ def brtarget : Operand<OtherVT> {
 
 def calltarget : Operand<i32> {
   let EncoderMethod = "getCallTargetOpValue";
+  let DecoderMethod = "DecodeCall";
 }
 
 // Operand for printing out a condition code.
@@ -577,8 +578,8 @@ let Uses = [FCC] in
 // This is the only Format 1 instruction
 let Uses = [O6],
     hasDelaySlot = 1, isCall = 1 in {
-  def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
-                    "call $dst", []> {
+  def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
+                    "call $disp", []> {
     bits<30> disp;
     let op = 1;
     let Inst{29-0} = disp;

Modified: llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt?rev=202577&r1=202576&r2=202577&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt Sat Mar  1 02:30:58 2014
@@ -170,3 +170,6 @@
 
 # CHECK: restore
 0x81 0xe8 0x00 0x00
+
+# CHECK: call 16
+0x40 0x00 0x00 0x04