[PATCH] [XCore] Target optimized library function __memcpy_4()

[Richard Osborne]

  Respect the AlwaysInline parameter in ​EmitTargetCodeForMemcpy.

  If AlwaysInline is set to true fallback to the target independent code.
  It is not possible to add a test for this since AlwaysInline is always set
  to false when EmitTargetCodeForMemcpy is called in the XCore backend.

Hi robertlytton,

http://llvm-reviews.chandlerc.com/D2871

CHANGE SINCE LAST DIFF
  http://llvm-reviews.chandlerc.com/D2871?vs=7322&id=7392#toc

Files:
  lib/Target/XCore/XCoreSelectionDAGInfo.cpp
  lib/Target/XCore/XCoreSelectionDAGInfo.h
  test/CodeGen/XCore/byVal.ll
  test/CodeGen/XCore/memcpy.ll

Index: lib/Target/XCore/XCoreSelectionDAGInfo.cpp
===================================================================
--- lib/Target/XCore/XCoreSelectionDAGInfo.cpp
+++ lib/Target/XCore/XCoreSelectionDAGInfo.cpp
@@ -21,3 +21,36 @@
 
 XCoreSelectionDAGInfo::~XCoreSelectionDAGInfo() {
 }
+
+SDValue XCoreSelectionDAGInfo::
+EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
+                        SDValue Dst, SDValue Src, SDValue Size, unsigned Align,
+                        bool isVolatile, bool AlwaysInline,
+                        MachinePointerInfo DstPtrInfo,
+                        MachinePointerInfo SrcPtrInfo) const
+{
+  unsigned SizeBitWidth = Size.getValueType().getSizeInBits();
+  // Call __memcpy_4 if the src, dst and size are all 4 byte aligned.
+  if (!AlwaysInline && (Align & 3) == 0 &&
+      DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) {
+    const TargetLowering &TLI = *DAG.getTarget().getTargetLowering();
+    TargetLowering::ArgListTy Args;
+    TargetLowering::ArgListEntry Entry;
+    Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext());
+    Entry.Node = Dst; Args.push_back(Entry);
+    Entry.Node = Src; Args.push_back(Entry);
+    Entry.Node = Size; Args.push_back(Entry);
+
+    TargetLowering::CallLoweringInfo
+    CLI(Chain, Type::getVoidTy(*DAG.getContext()), false, false, false, false,
+        0, TLI.getLibcallCallingConv(RTLIB::MEMCPY), /*isTailCall=*/false,
+        /*doesNotRet=*/false, /*isReturnValueUsed=*/false,
+        DAG.getExternalSymbol("__memcpy_4", TLI.getPointerTy()), Args, DAG, dl);
+    std::pair<SDValue,SDValue> CallResult =
+      TLI.LowerCallTo(CLI);
+    return CallResult.second;
+  }
+
+  // Otherwise have the target-independent code call memcpy.
+  return SDValue();
+}
Index: lib/Target/XCore/XCoreSelectionDAGInfo.h
===================================================================
--- lib/Target/XCore/XCoreSelectionDAGInfo.h
+++ lib/Target/XCore/XCoreSelectionDAGInfo.h
@@ -24,6 +24,15 @@
 public:
   explicit XCoreSelectionDAGInfo(const XCoreTargetMachine &TM);
   ~XCoreSelectionDAGInfo();
+
+  virtual SDValue
+  EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
+                          SDValue Chain,
+                          SDValue Op1, SDValue Op2,
+                          SDValue Op3, unsigned Align, bool isVolatile,
+                          bool AlwaysInline,
+                          MachinePointerInfo DstPtrInfo,
+                          MachinePointerInfo SrcPtrInfo) const;
 };
 
 }
Index: test/CodeGen/XCore/byVal.ll
===================================================================
--- test/CodeGen/XCore/byVal.ll
+++ test/CodeGen/XCore/byVal.ll
@@ -20,7 +20,7 @@
 ; CHECK: ldaw r5, sp[1]
 ; CHECK: ldc r2, 40
 ; CHECK: mov r0, r5
-; CHECK: bl memcpy
+; CHECK: bl __memcpy_4
 ; CHECK: mov r0, r5
 ; CHECK: bl f1
 ; CHECK: mov r0, r4
Index: test/CodeGen/XCore/memcpy.ll
===================================================================
--- /dev/null
+++ test/CodeGen/XCore/memcpy.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+; Optimize memcpy to __memcpy_4 if src, dst and size are all 4 byte aligned.
+define void @f1(i8* %dst, i8* %src, i32 %n) nounwind {
+; CHECK-LABEL: f1:
+; CHECK: bl __memcpy_4
+entry:
+  %0 = shl i32 %n, 2
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %0, i32 4, i1 false)
+  ret void
+}
+
+; Can't optimize - size is not a multiple of 4.
+define void @f2(i8* %dst, i8* %src, i32 %n) nounwind {
+; CHECK-LABEL: f2:
+; CHECK: bl memcpy
+entry:
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %n, i32 4, i1 false)
+  ret void
+}
+
+; Can't optimize - alignment is not a multiple of 4.
+define void @f3(i8* %dst, i8* %src, i32 %n) nounwind {
+; CHECK-LABEL: f3:
+; CHECK: bl memcpy
+entry:
+  %0 = shl i32 %n, 2
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 %0, i32 2, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D2871.2.patch
Type: text/x-patch
Size: 4051 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140227/41ec1683/attachment.bin>