[llvm] r202304 - Add a limit to the heuristic that register allocates instructions in local order.

[Renato Golin]

Hi Andrew,

I believe your patch broke a test on ARM's test-suite:

http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/5356

I'll revert your patch locally and run it again, to make sure it was it.

cheers,
--renato

On 26 February 2014 22:07, Andrew Trick <atrick at apple.com> wrote:
> Author: atrick
> Date: Wed Feb 26 16:07:26 2014
> New Revision: 202304
>
> URL: http://llvm.org/viewvc/llvm-project?rev=202304&view=rev
> Log:
> Add a limit to the heuristic that register allocates instructions in local order.
>
> This handles pathological cases in which we see 2x increase in spill
> code for large blocks (~50k instructions). I don't have a unit test
> for this behavior.
>
> Fixes rdar://16072279.
>
> Modified:
>     llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
>     llvm/trunk/test/CodeGen/X86/misched-matmul.ll
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=202304&r1=202303&r2=202304&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Wed Feb 26 16:07:26 2014
> @@ -454,12 +454,18 @@ void RAGreedy::enqueue(PQueue &CurQueue,
>      // everything else has been allocated.
>      Prio = Size;
>    } else {
> -    if (ExtraRegInfo[Reg].Stage == RS_Assign && !LI->empty() &&
> +    // Giant live ranges fall back to the global assignment heuristic, which
> +    // prevents excessive spilling in pathological cases.
> +    bool ReverseLocal = TRI->reverseLocalAssignment();
> +    bool ForceGlobal = !ReverseLocal &&
> +      (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
> +
> +    if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
>          LIS->intervalIsInOneMBB(*LI)) {
>        // Allocate original local ranges in linear instruction order. Since they
>        // are singly defined, this produces optimal coloring in the absence of
>        // global interference and other constraints.
> -      if (!TRI->reverseLocalAssignment())
> +      if (!ReverseLocal)
>          Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
>        else {
>          // Allocating bottom up may allow many short LRGs to be assigned first
>
> Modified: llvm/trunk/test/CodeGen/X86/misched-matmul.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-matmul.ll?rev=202304&r1=202303&r2=202304&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/misched-matmul.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/misched-matmul.ll Wed Feb 26 16:07:26 2014
> @@ -10,7 +10,7 @@
>  ; more complex cases.
>  ;
>  ; CHECK: @wrap_mul4
> -; CHECK: 23 regalloc - Number of spills inserted
> +; CHECK: 22 regalloc - Number of spills inserted
>
>  define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
>  entry:
>
>
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