[llvm] r202107 - Fix typos
Alp Toker
alp at nuanti.com
Mon Feb 24 20:21:16 PST 2014
Author: alp
Date: Mon Feb 24 22:21:15 2014
New Revision: 202107
URL: http://llvm.org/viewvc/llvm-project?rev=202107&view=rev
Log:
Fix typos
Modified:
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Transforms/Scalar/ConstantHoisting.cpp
llvm/trunk/test/MC/COFF/section-name-encoding.s
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=202107&r1=202106&r2=202107&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Feb 24 22:21:15 2014
@@ -1916,7 +1916,7 @@ RAGreedy::mayRecolorAllInterferences(uns
/// R3 is available.
/// Recoloring => vC = R1, vA = R2, vB = R3
///
-/// \p Order defines the prefered allocation order for \p VirtReg.
+/// \p Order defines the preferred allocation order for \p VirtReg.
/// \p NewRegs will contain any new virtual register that have been created
/// (split, spill) during the process and that must be assigned.
/// \p FixedRegisters contains all the virtual registers that cannot be
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=202107&r1=202106&r2=202107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Mon Feb 24 22:21:15 2014
@@ -3198,7 +3198,7 @@ def : Pat<(i64 (cttz (i64 DoubleRegs:$sr
// i8 -> i64 loads
-// We need a complexity of 120 here to overide preceeding handling of
+// We need a complexity of 120 here to override preceding handling of
// zextloadi8.
let Predicates = [HasV4T], AddedComplexity = 120 in {
def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
@@ -3220,7 +3220,7 @@ def: Pat <(i64 (sextloadi8 FoldGlobalAd
(i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
}
// i16 -> i64 loads
-// We need a complexity of 120 here to overide preceeding handling of
+// We need a complexity of 120 here to override preceding handling of
// zextloadi16.
let AddedComplexity = 120 in {
def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
@@ -3248,7 +3248,7 @@ def: Pat <(i64 (sextloadi16 FoldGlobalA
Requires<[HasV4T]>;
}
// i32->i64 loads
-// We need a complexity of 120 here to overide preceeding handling of
+// We need a complexity of 120 here to override preceding handling of
// zextloadi32.
let AddedComplexity = 120 in {
def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
Modified: llvm/trunk/lib/Transforms/Scalar/ConstantHoisting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ConstantHoisting.cpp?rev=202107&r1=202106&r2=202107&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ConstantHoisting.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ConstantHoisting.cpp Mon Feb 24 22:21:15 2014
@@ -454,7 +454,7 @@ bool ConstantHoisting::OptimizeConstants
// base constant.
FindBaseConstants();
- // Finaly hoist the base constant and emit materializating code for dependent
+ // Finally hoist the base constant and emit materializating code for dependent
// constants.
MadeChange |= EmitBaseConstants(F);
Modified: llvm/trunk/test/MC/COFF/section-name-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/COFF/section-name-encoding.s?rev=202107&r1=202106&r2=202107&view=diff
==============================================================================
--- llvm/trunk/test/MC/COFF/section-name-encoding.s (original)
+++ llvm/trunk/test/MC/COFF/section-name-encoding.s Mon Feb 24 22:21:15 2014
@@ -76,7 +76,7 @@ pad_sections_ex aaaaaaaaaaaaaaaaaaaaaaaa
// //AAmJa4 == 1000029 + 12 + (5 * (2 + (9 * 20 * 10 * 1000) + 1)) == 38*64^3 + 9*64^2 + 26*64 + 56
// v | | v ~~~~~~~~~~~~~~~~~~ v
-// seven_digit offset v v "p0" pad NUL seperator
+// seven_digit offset v v "p0" pad NUL separator
// "seven_digit\0" # of pad sections
//
// "2F 2F 41 41 6D 4A 61 34" is "//AAmJa4", which decodes to "0 0 38 9 26 56".
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