[llvm] r202024 - Add AArch64 big endian Target (aarch64_be)
Renato Golin
renato.golin at linaro.org
Mon Feb 24 05:45:08 PST 2014
Hi Christian,
Please keep you patches whitespace-change free. It makes it hard to
keep track of who changed what.
cheers,
--renato
On 24 February 2014 11:34, Christian Pirker <cpirker at a-bix.com> wrote:
> Author: cpirker
> Date: Mon Feb 24 05:34:50 2014
> New Revision: 202024
>
> URL: http://llvm.org/viewvc/llvm-project?rev=202024&view=rev
> Log:
> Add AArch64 big endian Target (aarch64_be)
>
> Modified:
> llvm/trunk/include/llvm/ADT/Triple.h
> llvm/trunk/lib/Support/Triple.cpp
> llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
> llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
>
> Modified: llvm/trunk/include/llvm/ADT/Triple.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/ADT/Triple.h (original)
> +++ llvm/trunk/include/llvm/ADT/Triple.h Mon Feb 24 05:34:50 2014
> @@ -46,32 +46,33 @@ public:
> enum ArchType {
> UnknownArch,
>
> - arm, // ARM: arm, armv.*, xscale
> - aarch64, // AArch64: aarch64
> - hexagon, // Hexagon: hexagon
> - mips, // MIPS: mips, mipsallegrex
> - mipsel, // MIPSEL: mipsel, mipsallegrexel
> - mips64, // MIPS64: mips64
> - mips64el,// MIPS64EL: mips64el
> - msp430, // MSP430: msp430
> - ppc, // PPC: powerpc
> - ppc64, // PPC64: powerpc64, ppu
> - ppc64le, // PPC64LE: powerpc64le
> - r600, // R600: AMD GPUs HD2XXX - HD6XXX
> - sparc, // Sparc: sparc
> - sparcv9, // Sparcv9: Sparcv9
> - systemz, // SystemZ: s390x
> - tce, // TCE (http://tce.cs.tut.fi/): tce
> - thumb, // Thumb: thumb, thumbv.*
> - x86, // X86: i[3-9]86
> - x86_64, // X86-64: amd64, x86_64
> - xcore, // XCore: xcore
> - nvptx, // NVPTX: 32-bit
> - nvptx64, // NVPTX: 64-bit
> - le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
> - amdil, // amdil: amd IL
> - spir, // SPIR: standard portable IR for OpenCL 32-bit version
> - spir64 // SPIR: standard portable IR for OpenCL 64-bit version
> + arm, // ARM: arm, armv.*, xscale
> + aarch64, // AArch64 (little endian): aarch64
> + aarch64_be, // AArch64 (big endian): aarch64_be
> + hexagon, // Hexagon: hexagon
> + mips, // MIPS: mips, mipsallegrex
> + mipsel, // MIPSEL: mipsel, mipsallegrexel
> + mips64, // MIPS64: mips64
> + mips64el, // MIPS64EL: mips64el
> + msp430, // MSP430: msp430
> + ppc, // PPC: powerpc
> + ppc64, // PPC64: powerpc64, ppu
> + ppc64le, // PPC64LE: powerpc64le
> + r600, // R600: AMD GPUs HD2XXX - HD6XXX
> + sparc, // Sparc: sparc
> + sparcv9, // Sparcv9: Sparcv9
> + systemz, // SystemZ: s390x
> + tce, // TCE (http://tce.cs.tut.fi/): tce
> + thumb, // Thumb: thumb, thumbv.*
> + x86, // X86: i[3-9]86
> + x86_64, // X86-64: amd64, x86_64
> + xcore, // XCore: xcore
> + nvptx, // NVPTX: 32-bit
> + nvptx64, // NVPTX: 64-bit
> + le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
> + amdil, // amdil: amd IL
> + spir, // SPIR: standard portable IR for OpenCL 32-bit version
> + spir64 // SPIR: standard portable IR for OpenCL 64-bit version
> };
> enum VendorType {
> UnknownVendor,
>
> Modified: llvm/trunk/lib/Support/Triple.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Support/Triple.cpp (original)
> +++ llvm/trunk/lib/Support/Triple.cpp Mon Feb 24 05:34:50 2014
> @@ -19,32 +19,33 @@ const char *Triple::getArchTypeName(Arch
> switch (Kind) {
> case UnknownArch: return "unknown";
>
> - case aarch64: return "aarch64";
> - case arm: return "arm";
> - case hexagon: return "hexagon";
> - case mips: return "mips";
> - case mipsel: return "mipsel";
> - case mips64: return "mips64";
> - case mips64el:return "mips64el";
> - case msp430: return "msp430";
> - case ppc64: return "powerpc64";
> - case ppc64le: return "powerpc64le";
> - case ppc: return "powerpc";
> - case r600: return "r600";
> - case sparc: return "sparc";
> - case sparcv9: return "sparcv9";
> - case systemz: return "s390x";
> - case tce: return "tce";
> - case thumb: return "thumb";
> - case x86: return "i386";
> - case x86_64: return "x86_64";
> - case xcore: return "xcore";
> - case nvptx: return "nvptx";
> - case nvptx64: return "nvptx64";
> - case le32: return "le32";
> - case amdil: return "amdil";
> - case spir: return "spir";
> - case spir64: return "spir64";
> + case aarch64: return "aarch64";
> + case aarch64_be: return "aarch64_be";
> + case arm: return "arm";
> + case hexagon: return "hexagon";
> + case mips: return "mips";
> + case mipsel: return "mipsel";
> + case mips64: return "mips64";
> + case mips64el: return "mips64el";
> + case msp430: return "msp430";
> + case ppc64: return "powerpc64";
> + case ppc64le: return "powerpc64le";
> + case ppc: return "powerpc";
> + case r600: return "r600";
> + case sparc: return "sparc";
> + case sparcv9: return "sparcv9";
> + case systemz: return "s390x";
> + case tce: return "tce";
> + case thumb: return "thumb";
> + case x86: return "i386";
> + case x86_64: return "x86_64";
> + case xcore: return "xcore";
> + case nvptx: return "nvptx";
> + case nvptx64: return "nvptx64";
> + case le32: return "le32";
> + case amdil: return "amdil";
> + case spir: return "spir";
> + case spir64: return "spir64";
> }
>
> llvm_unreachable("Invalid ArchType!");
> @@ -55,40 +56,41 @@ const char *Triple::getArchTypePrefix(Ar
> default:
> return 0;
>
> - case aarch64: return "aarch64";
> + case aarch64:
> + case aarch64_be: return "aarch64";
>
> case arm:
> - case thumb: return "arm";
> + case thumb: return "arm";
>
> case ppc64:
> case ppc64le:
> - case ppc: return "ppc";
> + case ppc: return "ppc";
>
> case mips:
> case mipsel:
> case mips64:
> - case mips64el:return "mips";
> + case mips64el: return "mips";
>
> - case hexagon: return "hexagon";
> + case hexagon: return "hexagon";
>
> - case r600: return "r600";
> + case r600: return "r600";
>
> case sparcv9:
> - case sparc: return "sparc";
> + case sparc: return "sparc";
>
> - case systemz: return "systemz";
> + case systemz: return "systemz";
>
> case x86:
> - case x86_64: return "x86";
> + case x86_64: return "x86";
>
> - case xcore: return "xcore";
> + case xcore: return "xcore";
>
> - case nvptx: return "nvptx";
> - case nvptx64: return "nvptx";
> - case le32: return "le32";
> - case amdil: return "amdil";
> - case spir: return "spir";
> - case spir64: return "spir";
> + case nvptx: return "nvptx";
> + case nvptx64: return "nvptx";
> + case le32: return "le32";
> + case amdil: return "amdil";
> + case spir: return "spir";
> + case spir64: return "spir";
> }
> }
>
> @@ -163,6 +165,7 @@ const char *Triple::getEnvironmentTypeNa
> Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
> return StringSwitch<Triple::ArchType>(Name)
> .Case("aarch64", aarch64)
> + .Case("aarch64_be", aarch64_be)
> .Case("arm", arm)
> .Case("mips", mips)
> .Case("mipsel", mipsel)
> @@ -228,6 +231,7 @@ static Triple::ArchType parseArch(String
> .Cases("powerpc64", "ppu", Triple::ppc64)
> .Case("powerpc64le", Triple::ppc64le)
> .Case("aarch64", Triple::aarch64)
> + .Case("aarch64_be", Triple::aarch64_be)
> .Cases("arm", "xscale", Triple::arm)
> // FIXME: It would be good to replace these with explicit names for all the
> // various suffixes supported.
> @@ -695,6 +699,7 @@ static unsigned getArchPointerBitWidth(l
> return 32;
>
> case llvm::Triple::aarch64:
> + case llvm::Triple::aarch64_be:
> case llvm::Triple::mips64:
> case llvm::Triple::mips64el:
> case llvm::Triple::nvptx64:
> @@ -726,6 +731,7 @@ Triple Triple::get32BitArchVariant() con
> switch (getArch()) {
> case Triple::UnknownArch:
> case Triple::aarch64:
> + case Triple::aarch64_be:
> case Triple::msp430:
> case Triple::systemz:
> case Triple::ppc64le:
> @@ -778,6 +784,7 @@ Triple Triple::get64BitArchVariant() con
> break;
>
> case Triple::aarch64:
> + case Triple::aarch64_be:
> case Triple::spir64:
> case Triple::mips64:
> case Triple::mips64el:
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Mon Feb 24 05:34:50 2014
> @@ -296,6 +296,7 @@ bool AArch64AsmPrinter::runOnMachineFunc
>
> // Force static initialization.
> extern "C" void LLVMInitializeAArch64AsmPrinter() {
> - RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64Target);
> + RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
> + RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
> }
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Mon Feb 24 05:34:50 2014
> @@ -28,9 +28,11 @@ using namespace llvm;
> // Pin the vtable to this file.
> void AArch64Subtarget::anchor() {}
>
> -AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS)
> +AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
> + bool LittleEndian)
> : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false),
> - HasCrypto(false), TargetTriple(TT), CPUString(CPU) {
> + HasCrypto(false), TargetTriple(TT), CPUString(CPU),
> + IsLittleEndian(LittleEndian) {
>
> initializeSubtargetFeatures(CPU, FS);
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Mon Feb 24 05:34:50 2014
> @@ -39,6 +39,9 @@ protected:
> /// CPUString - String name of used CPU.
> std::string CPUString;
>
> + /// IsLittleEndian - The target is Little Endian
> + bool IsLittleEndian;
> +
> private:
> void initializeSubtargetFeatures(StringRef CPU, StringRef FS);
>
> @@ -46,7 +49,8 @@ public:
> /// This constructor initializes the data members to match that
> /// of the specified triple.
> ///
> - AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS);
> + AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
> + bool LittleEndian);
>
> virtual bool enableMachineScheduler() const {
> return true;
> @@ -65,6 +69,8 @@ public:
> bool hasNEON() const { return HasNEON; }
> bool hasCrypto() const { return HasCrypto; }
>
> + bool isLittle() const { return IsLittleEndian; }
> +
> const std::string & getCPUString() const { return CPUString; }
> };
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Mon Feb 24 05:34:50 2014
> @@ -23,24 +23,46 @@
> using namespace llvm;
>
> extern "C" void LLVMInitializeAArch64Target() {
> - RegisterTargetMachine<AArch64TargetMachine> X(TheAArch64Target);
> + RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
> + RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
> }
>
> AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
> StringRef CPU, StringRef FS,
> const TargetOptions &Options,
> Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL)
> + CodeGenOpt::Level OL,
> + bool LittleEndian)
> : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
> - Subtarget(TT, CPU, FS),
> + Subtarget(TT, CPU, FS, LittleEndian),
> InstrInfo(Subtarget),
> - DL("e-m:e-i64:64-i128:128-n32:64-S128"),
> + DL(LittleEndian ?
> + "e-m:e-i64:64-i128:128-n32:64-S128" :
> + "E-m:e-i64:64-i128:128-n32:64-S128"),
> TLInfo(*this),
> TSInfo(*this),
> FrameLowering(Subtarget) {
> initAsmInfo();
> }
>
> +void AArch64leTargetMachine::anchor() { }
> +
> +AArch64leTargetMachine::
> +AArch64leTargetMachine(const Target &T, StringRef TT,
> + StringRef CPU, StringRef FS, const TargetOptions &Options,
> + Reloc::Model RM, CodeModel::Model CM,
> + CodeGenOpt::Level OL)
> + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
> +
> +void AArch64beTargetMachine::anchor() { }
> +
> +AArch64beTargetMachine::
> +AArch64beTargetMachine(const Target &T, StringRef TT,
> + StringRef CPU, StringRef FS, const TargetOptions &Options,
> + Reloc::Model RM, CodeModel::Model CM,
> + CodeGenOpt::Level OL)
> + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
> +
> void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
> // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
> // allows the AArch64 pass to delegate to the target independent layer when
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Mon Feb 24 05:34:50 2014
> @@ -36,7 +36,8 @@ public:
> AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
> StringRef FS, const TargetOptions &Options,
> Reloc::Model RM, CodeModel::Model CM,
> - CodeGenOpt::Level OL);
> + CodeGenOpt::Level OL,
> + bool LittleEndian);
>
> const AArch64InstrInfo *getInstrInfo() const {
> return &InstrInfo;
> @@ -66,6 +67,28 @@ public:
> virtual void addAnalysisPasses(PassManagerBase &PM);
> };
>
> -}
> +// AArch64leTargetMachine - AArch64 little endian target machine.
> +//
> +class AArch64leTargetMachine : public AArch64TargetMachine {
> + virtual void anchor();
> +public:
> + AArch64leTargetMachine(const Target &T, StringRef TT,
> + StringRef CPU, StringRef FS, const TargetOptions &Options,
> + Reloc::Model RM, CodeModel::Model CM,
> + CodeGenOpt::Level OL);
> +};
> +
> +// AArch64beTargetMachine - AArch64 big endian target machine.
> +//
> +class AArch64beTargetMachine : public AArch64TargetMachine {
> + virtual void anchor();
> +public:
> + AArch64beTargetMachine(const Target &T, StringRef TT,
> + StringRef CPU, StringRef FS, const TargetOptions &Options,
> + Reloc::Model RM, CodeModel::Model CM,
> + CodeGenOpt::Level OL);
> +};
> +
> +} // End llvm namespace
>
> #endif
>
> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Mon Feb 24 05:34:50 2014
> @@ -2661,7 +2661,8 @@ void AArch64Operand::dump() const {
>
> /// Force static initialization.
> extern "C" void LLVMInitializeAArch64AsmParser() {
> - RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64Target);
> + RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64leTarget);
> + RegisterMCAsmParser<AArch64AsmParser> Y(TheAArch64beTarget);
> }
>
> #define GET_REGISTER_MATCHER
>
> Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Mon Feb 24 05:34:50 2014
> @@ -996,7 +996,9 @@ static MCDisassembler *createAArch64Disa
> }
>
> extern "C" void LLVMInitializeAArch64Disassembler() {
> - TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
> + TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
> + createAArch64Disassembler);
> + TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
> createAArch64Disassembler);
> }
>
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp Mon Feb 24 05:34:50 2014
> @@ -79,11 +79,12 @@ static uint64_t adjustFixupValue(unsigne
> namespace {
>
> class ELFAArch64AsmBackend : public AArch64AsmBackend {
> -public:
> uint8_t OSABI;
> + bool IsLittle; // Big or little endian
> +public:
> ELFAArch64AsmBackend(const Target &T, const StringRef TT,
> - uint8_t _OSABI)
> - : AArch64AsmBackend(T, TT), OSABI(_OSABI) { }
> + uint8_t _OSABI, bool isLittle)
> + : AArch64AsmBackend(T, TT), OSABI(_OSABI), IsLittle(isLittle) { }
>
> bool fixupNeedsRelaxation(const MCFixup &Fixup,
> uint64_t Value,
> @@ -200,7 +201,7 @@ public:
> }
>
> MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
> - return createAArch64ELFObjectWriter(OS, OSABI);
> + return createAArch64ELFObjectWriter(OS, OSABI, IsLittle);
> }
> };
>
> @@ -578,8 +579,15 @@ static uint64_t adjustFixupValue(unsigne
> }
>
> MCAsmBackend *
> -llvm::createAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
> +llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> + StringRef TT, StringRef CPU) {
> + Triple TheTriple(TT);
> + return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ true);
> +}
> +
> +MCAsmBackend *
> +llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI,
> StringRef TT, StringRef CPU) {
> Triple TheTriple(TT);
> - return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS());
> + return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ false);
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp Mon Feb 24 05:34:50 2014
> @@ -23,7 +23,7 @@ using namespace llvm;
> namespace {
> class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
> public:
> - AArch64ELFObjectWriter(uint8_t OSABI);
> + AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
>
> virtual ~AArch64ELFObjectWriter();
>
> @@ -35,7 +35,7 @@ private:
> };
> }
>
> -AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI)
> +AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian)
> : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
> /*HasRelocationAddend*/ true)
> {}
> @@ -286,7 +286,8 @@ unsigned AArch64ELFObjectWriter::GetRelo
> }
>
> MCObjectWriter *llvm::createAArch64ELFObjectWriter(raw_ostream &OS,
> - uint8_t OSABI) {
> - MCELFObjectTargetWriter *MOTW = new AArch64ELFObjectWriter(OSABI);
> - return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true);
> + uint8_t OSABI,
> + bool IsLittleEndian) {
> + MCELFObjectTargetWriter *MOTW = new AArch64ELFObjectWriter(OSABI, IsLittleEndian);
> + return createELFObjectWriter(MOTW, OS, IsLittleEndian);
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp Mon Feb 24 05:34:50 2014
> @@ -12,10 +12,15 @@
> //===----------------------------------------------------------------------===//
>
> #include "AArch64MCAsmInfo.h"
> +#include "llvm/ADT/Triple.h"
>
> using namespace llvm;
>
> -AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() {
> +AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo(StringRef TT) {
> + Triple TheTriple(TT);
> + if (TheTriple.getArch() == Triple::aarch64_be)
> + IsLittleEndian = false;
> +
> PointerSize = 8;
>
> // ".comm align is in bytes but .align is pow-2."
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h Mon Feb 24 05:34:50 2014
> @@ -19,7 +19,7 @@
> namespace llvm {
>
> struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
> - explicit AArch64ELFMCAsmInfo();
> + explicit AArch64ELFMCAsmInfo(StringRef TT);
> private:
> virtual void anchor();
> };
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp Mon Feb 24 05:34:50 2014
> @@ -61,7 +61,7 @@ static MCAsmInfo *createAArch64MCAsmInfo
> StringRef TT) {
> Triple TheTriple(TT);
>
> - MCAsmInfo *MAI = new AArch64ELFMCAsmInfo();
> + MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
> unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
> MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
> MAI->addInitialFrameState(Inst);
> @@ -161,42 +161,61 @@ static MCInstrAnalysis *createAArch64MCI
>
> extern "C" void LLVMInitializeAArch64TargetMC() {
> // Register the MC asm info.
> - RegisterMCAsmInfoFn A(TheAArch64Target, createAArch64MCAsmInfo);
> + RegisterMCAsmInfoFn A(TheAArch64leTarget, createAArch64MCAsmInfo);
> + RegisterMCAsmInfoFn B(TheAArch64beTarget, createAArch64MCAsmInfo);
>
> // Register the MC codegen info.
> - TargetRegistry::RegisterMCCodeGenInfo(TheAArch64Target,
> + TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
> + createAArch64MCCodeGenInfo);
> + TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
> createAArch64MCCodeGenInfo);
>
> // Register the MC instruction info.
> - TargetRegistry::RegisterMCInstrInfo(TheAArch64Target,
> + TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget,
> + createAArch64MCInstrInfo);
> + TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget,
> createAArch64MCInstrInfo);
>
> // Register the MC register info.
> - TargetRegistry::RegisterMCRegInfo(TheAArch64Target,
> + TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget,
> + createAArch64MCRegisterInfo);
> + TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget,
> createAArch64MCRegisterInfo);
>
> // Register the MC subtarget info.
> using AArch64_MC::createAArch64MCSubtargetInfo;
> - TargetRegistry::RegisterMCSubtargetInfo(TheAArch64Target,
> + TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
> + createAArch64MCSubtargetInfo);
> + TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
> createAArch64MCSubtargetInfo);
>
> // Register the MC instruction analyzer.
> - TargetRegistry::RegisterMCInstrAnalysis(TheAArch64Target,
> + TargetRegistry::RegisterMCInstrAnalysis(TheAArch64leTarget,
> + createAArch64MCInstrAnalysis);
> + TargetRegistry::RegisterMCInstrAnalysis(TheAArch64beTarget,
> createAArch64MCInstrAnalysis);
>
> // Register the MC Code Emitter
> - TargetRegistry::RegisterMCCodeEmitter(TheAArch64Target,
> + TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
> + createAArch64MCCodeEmitter);
> + TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
> createAArch64MCCodeEmitter);
>
> // Register the asm backend.
> - TargetRegistry::RegisterMCAsmBackend(TheAArch64Target,
> - createAArch64AsmBackend);
> + TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget,
> + createAArch64leAsmBackend);
> + TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
> + createAArch64beAsmBackend);
>
> // Register the object streamer.
> - TargetRegistry::RegisterMCObjectStreamer(TheAArch64Target,
> + TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget,
> + createMCStreamer);
> + TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget,
> createMCStreamer);
>
> // Register the MCInstPrinter.
> - TargetRegistry::RegisterMCInstPrinter(TheAArch64Target,
> + TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
> + createAArch64MCInstPrinter);
> + TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
> createAArch64MCInstPrinter);
> }
>
> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h (original)
> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h Mon Feb 24 05:34:50 2014
> @@ -28,7 +28,8 @@ class StringRef;
> class Target;
> class raw_ostream;
>
> -extern Target TheAArch64Target;
> +extern Target TheAArch64leTarget;
> +extern Target TheAArch64beTarget;
>
> namespace AArch64_MC {
> MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU,
> @@ -41,11 +42,16 @@ MCCodeEmitter *createAArch64MCCodeEmitte
> MCContext &Ctx);
>
> MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS,
> - uint8_t OSABI);
> + uint8_t OSABI,
> + bool IsLittleEndian);
>
> -MCAsmBackend *createAArch64AsmBackend(const Target &T,
> - const MCRegisterInfo &MRI,
> - StringRef TT, StringRef CPU);
> +MCAsmBackend *createAArch64leAsmBackend(const Target &T,
> + const MCRegisterInfo &MRI,
> + StringRef TT, StringRef CPU);
> +
> +MCAsmBackend *createAArch64beAsmBackend(const Target &T,
> + const MCRegisterInfo &MRI,
> + StringRef TT, StringRef CPU);
>
> } // End llvm namespace
>
>
> Modified: llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp?rev=202024&r1=202023&r2=202024&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp Mon Feb 24 05:34:50 2014
> @@ -16,9 +16,12 @@
> #include "llvm/Support/TargetRegistry.h"
> using namespace llvm;
>
> -Target llvm::TheAArch64Target;
> +Target llvm::TheAArch64leTarget;
> +Target llvm::TheAArch64beTarget;
>
> extern "C" void LLVMInitializeAArch64TargetInfo() {
> RegisterTarget<Triple::aarch64, /*HasJIT=*/true>
> - X(TheAArch64Target, "aarch64", "AArch64 (ARM 64-bit target)");
> + X(TheAArch64leTarget, "aarch64", "AArch64 (ARM 64-bit little endian target)");
> + RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true>
> + Y(TheAArch64beTarget, "aarch64_be", "AArch64 (ARM 64-bit big endian target)");
> }
>
>
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