Add AArch64 big endian Target (aarch64_be)
Christian Pirker
cpirker at a-bix.com
Thu Feb 20 08:04:59 PST 2014
Hi all,
This patch adds a target machine class for little and big endian AArch64.
This includes a modification to the data layout string.
(A corresponding target description has been committed to cfe-commits.)
Please review.
Thanks,
Christian
Modified:
include/llvm/ADT/Triple.h
lib/Support/Triple.cpp
lib/Target/AArch64/AArch64AsmPrinter.cpp
lib/Target/AArch64/AArch64Subtarget.cpp
lib/Target/AArch64/AArch64Subtarget.h
lib/Target/AArch64/AArch64TargetMachine.cpp
lib/Target/AArch64/AArch64TargetMachine.h
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
-------------- next part --------------
Index: include/llvm/ADT/Triple.h
===================================================================
--- include/llvm/ADT/Triple.h (revision 201559)
+++ include/llvm/ADT/Triple.h (working copy)
@@ -48,6 +48,7 @@
arm, // ARM: arm, armv.*, xscale
aarch64, // AArch64: aarch64
+ aarch64_be, // AArch64 (big endian): aarch64_be
hexagon, // Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex
mipsel, // MIPSEL: mipsel, mipsallegrexel
Index: lib/Support/Triple.cpp
===================================================================
--- lib/Support/Triple.cpp (revision 201559)
+++ lib/Support/Triple.cpp (working copy)
@@ -20,6 +20,7 @@
case UnknownArch: return "unknown";
case aarch64: return "aarch64";
+ case aarch64_be:return "aarch64_be";
case arm: return "arm";
case hexagon: return "hexagon";
case mips: return "mips";
@@ -55,7 +56,8 @@
default:
return 0;
- case aarch64: return "aarch64";
+ case aarch64:
+ case aarch64_be:return "aarch64";
case arm:
case thumb: return "arm";
@@ -163,6 +165,7 @@
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
return StringSwitch<Triple::ArchType>(Name)
.Case("aarch64", aarch64)
+ .Case("aarch64_be", aarch64_be)
.Case("arm", arm)
.Case("mips", mips)
.Case("mipsel", mipsel)
@@ -228,6 +231,7 @@
.Cases("powerpc64", "ppu", Triple::ppc64)
.Case("powerpc64le", Triple::ppc64le)
.Case("aarch64", Triple::aarch64)
+ .Case("aarch64_be", Triple::aarch64_be)
.Cases("arm", "xscale", Triple::arm)
// FIXME: It would be good to replace these with explicit names for all the
// various suffixes supported.
@@ -695,6 +699,7 @@
return 32;
case llvm::Triple::aarch64:
+ case llvm::Triple::aarch64_be:
case llvm::Triple::mips64:
case llvm::Triple::mips64el:
case llvm::Triple::nvptx64:
@@ -726,6 +731,7 @@
switch (getArch()) {
case Triple::UnknownArch:
case Triple::aarch64:
+ case Triple::aarch64_be:
case Triple::msp430:
case Triple::systemz:
case Triple::ppc64le:
@@ -778,6 +784,7 @@
break;
case Triple::aarch64:
+ case Triple::aarch64_be:
case Triple::spir64:
case Triple::mips64:
case Triple::mips64el:
Index: lib/Target/AArch64/AArch64AsmPrinter.cpp
===================================================================
--- lib/Target/AArch64/AArch64AsmPrinter.cpp (revision 201559)
+++ lib/Target/AArch64/AArch64AsmPrinter.cpp (working copy)
@@ -296,6 +296,7 @@
// Force static initialization.
extern "C" void LLVMInitializeAArch64AsmPrinter() {
- RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64Target);
+ RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
+ RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
}
Index: lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- lib/Target/AArch64/AArch64Subtarget.cpp (revision 201559)
+++ lib/Target/AArch64/AArch64Subtarget.cpp (working copy)
@@ -28,9 +28,9 @@
// Pin the vtable to this file.
void AArch64Subtarget::anchor() {}
-AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS)
+AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS, bool little)
: AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false),
- HasCrypto(false), TargetTriple(TT), CPUString(CPU) {
+ HasCrypto(false), TargetTriple(TT), CPUString(CPU), IsLittle(little) {
initializeSubtargetFeatures(CPU, FS);
}
Index: lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- lib/Target/AArch64/AArch64Subtarget.h (revision 201559)
+++ lib/Target/AArch64/AArch64Subtarget.h (working copy)
@@ -39,6 +39,9 @@
/// CPUString - String name of used CPU.
std::string CPUString;
+ /// IsLittle - The target is Little Endian
+ bool IsLittle;
+
private:
void initializeSubtargetFeatures(StringRef CPU, StringRef FS);
@@ -46,7 +49,7 @@
/// This constructor initializes the data members to match that
/// of the specified triple.
///
- AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS);
+ AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS, bool little);
virtual bool enableMachineScheduler() const {
return true;
@@ -65,6 +68,8 @@
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
+ bool isLittle() const { return IsLittle; }
+
const std::string & getCPUString() const { return CPUString; }
};
} // End llvm namespace
Index: lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetMachine.cpp (revision 201559)
+++ lib/Target/AArch64/AArch64TargetMachine.cpp (working copy)
@@ -23,24 +23,46 @@
using namespace llvm;
extern "C" void LLVMInitializeAArch64Target() {
- RegisterTargetMachine<AArch64TargetMachine> X(TheAArch64Target);
+ RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
+ RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
}
AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL)
+ CodeGenOpt::Level OL,
+ bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- Subtarget(TT, CPU, FS),
+ Subtarget(TT, CPU, FS, isLittle),
InstrInfo(Subtarget),
- DL("e-m:e-i64:64-i128:128-n32:64-S128"),
+ DL(isLittle ?
+ "e-m:e-i64:64-i128:128-n32:64-S128" :
+ "E-m:e-i64:64-i128:128-n32:64-S128"),
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
}
+void AArch64leTargetMachine::anchor() { }
+
+AArch64leTargetMachine::
+AArch64leTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+
+void AArch64beTargetMachine::anchor() { }
+
+AArch64beTargetMachine::
+AArch64beTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+
namespace {
/// AArch64 Code Generator Pass Configuration Options.
class AArch64PassConfig : public TargetPassConfig {
Index: lib/Target/AArch64/AArch64TargetMachine.h
===================================================================
--- lib/Target/AArch64/AArch64TargetMachine.h (revision 201559)
+++ lib/Target/AArch64/AArch64TargetMachine.h (working copy)
@@ -36,7 +36,8 @@
AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL);
+ CodeGenOpt::Level OL,
+ bool isLittle);
const AArch64InstrInfo *getInstrInfo() const {
return &InstrInfo;
@@ -64,6 +65,28 @@
TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
-}
+// AArch64leTargetMachine - AArch64 little endian target machine.
+//
+class AArch64leTargetMachine : public AArch64TargetMachine {
+ virtual void anchor();
+public:
+ AArch64leTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+};
+// AArch64beTargetMachine - AArch64 big endian target machine.
+//
+class AArch64beTargetMachine : public AArch64TargetMachine {
+ virtual void anchor();
+public:
+ AArch64beTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+};
+
+} // End llvm namespace
+
#endif
Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (revision 201559)
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (working copy)
@@ -2661,7 +2661,8 @@
/// Force static initialization.
extern "C" void LLVMInitializeAArch64AsmParser() {
- RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64Target);
+ RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64leTarget);
+ RegisterMCAsmParser<AArch64AsmParser> Y(TheAArch64beTarget);
}
#define GET_REGISTER_MATCHER
Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (revision 201559)
+++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (working copy)
@@ -996,8 +996,10 @@
}
extern "C" void LLVMInitializeAArch64Disassembler() {
- TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
+ TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
createAArch64Disassembler);
+ TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
+ createAArch64Disassembler);
}
template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp (working copy)
@@ -79,11 +79,12 @@
namespace {
class ELFAArch64AsmBackend : public AArch64AsmBackend {
+ uint8_t OSABI;
+ bool IsLittle; // Big or little endian
public:
- uint8_t OSABI;
ELFAArch64AsmBackend(const Target &T, const StringRef TT,
- uint8_t _OSABI)
- : AArch64AsmBackend(T, TT), OSABI(_OSABI) { }
+ uint8_t _OSABI, bool isLittle)
+ : AArch64AsmBackend(T, TT), OSABI(_OSABI), IsLittle(isLittle) { }
bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value,
@@ -200,7 +201,7 @@
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createAArch64ELFObjectWriter(OS, OSABI);
+ return createAArch64ELFObjectWriter(OS, OSABI, IsLittle);
}
};
@@ -578,8 +579,15 @@
}
MCAsmBackend *
-llvm::createAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
+llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) {
Triple TheTriple(TT);
- return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS());
+ return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ true);
}
+
+MCAsmBackend *
+llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI,
+ StringRef TT, StringRef CPU) {
+ Triple TheTriple(TT);
+ return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ false);
+}
Index: lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp (working copy)
@@ -23,7 +23,7 @@
namespace {
class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
public:
- AArch64ELFObjectWriter(uint8_t OSABI);
+ AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
virtual ~AArch64ELFObjectWriter();
@@ -35,7 +35,7 @@
};
}
-AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI)
+AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian)
: MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
/*HasRelocationAddend*/ true)
{}
@@ -286,7 +286,8 @@
}
MCObjectWriter *llvm::createAArch64ELFObjectWriter(raw_ostream &OS,
- uint8_t OSABI) {
- MCELFObjectTargetWriter *MOTW = new AArch64ELFObjectWriter(OSABI);
- return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true);
+ uint8_t OSABI,
+ bool IsLittleEndian) {
+ MCELFObjectTargetWriter *MOTW = new AArch64ELFObjectWriter(OSABI, IsLittleEndian);
+ return createELFObjectWriter(MOTW, OS, IsLittleEndian);
}
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp (working copy)
@@ -12,10 +12,15 @@
//===----------------------------------------------------------------------===//
#include "AArch64MCAsmInfo.h"
+#include "llvm/ADT/Triple.h"
using namespace llvm;
-AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() {
+AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo(StringRef TT) {
+ Triple TheTriple(TT);
+ if (TheTriple.getArch() == Triple::aarch64_be)
+ IsLittleEndian = false;
+
PointerSize = 8;
// ".comm align is in bytes but .align is pow-2."
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h (working copy)
@@ -19,7 +19,7 @@
namespace llvm {
struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
- explicit AArch64ELFMCAsmInfo();
+ explicit AArch64ELFMCAsmInfo(StringRef TT);
private:
virtual void anchor();
};
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp (working copy)
@@ -61,7 +61,7 @@
StringRef TT) {
Triple TheTriple(TT);
- MCAsmInfo *MAI = new AArch64ELFMCAsmInfo();
+ MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
MAI->addInitialFrameState(Inst);
@@ -161,42 +161,61 @@
extern "C" void LLVMInitializeAArch64TargetMC() {
// Register the MC asm info.
- RegisterMCAsmInfoFn A(TheAArch64Target, createAArch64MCAsmInfo);
+ RegisterMCAsmInfoFn A(TheAArch64leTarget, createAArch64MCAsmInfo);
+ RegisterMCAsmInfoFn B(TheAArch64beTarget, createAArch64MCAsmInfo);
// Register the MC codegen info.
- TargetRegistry::RegisterMCCodeGenInfo(TheAArch64Target,
+ TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
createAArch64MCCodeGenInfo);
+ TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
+ createAArch64MCCodeGenInfo);
// Register the MC instruction info.
- TargetRegistry::RegisterMCInstrInfo(TheAArch64Target,
+ TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget,
createAArch64MCInstrInfo);
+ TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget,
+ createAArch64MCInstrInfo);
// Register the MC register info.
- TargetRegistry::RegisterMCRegInfo(TheAArch64Target,
+ TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget,
createAArch64MCRegisterInfo);
+ TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget,
+ createAArch64MCRegisterInfo);
// Register the MC subtarget info.
using AArch64_MC::createAArch64MCSubtargetInfo;
- TargetRegistry::RegisterMCSubtargetInfo(TheAArch64Target,
+ TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
createAArch64MCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
+ createAArch64MCSubtargetInfo);
// Register the MC instruction analyzer.
- TargetRegistry::RegisterMCInstrAnalysis(TheAArch64Target,
+ TargetRegistry::RegisterMCInstrAnalysis(TheAArch64leTarget,
createAArch64MCInstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(TheAArch64beTarget,
+ createAArch64MCInstrAnalysis);
// Register the MC Code Emitter
- TargetRegistry::RegisterMCCodeEmitter(TheAArch64Target,
+ TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
createAArch64MCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
+ createAArch64MCCodeEmitter);
// Register the asm backend.
- TargetRegistry::RegisterMCAsmBackend(TheAArch64Target,
- createAArch64AsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget,
+ createAArch64leAsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
+ createAArch64beAsmBackend);
// Register the object streamer.
- TargetRegistry::RegisterMCObjectStreamer(TheAArch64Target,
+ TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget,
createMCStreamer);
+ TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget,
+ createMCStreamer);
// Register the MCInstPrinter.
- TargetRegistry::RegisterMCInstPrinter(TheAArch64Target,
+ TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
createAArch64MCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
+ createAArch64MCInstPrinter);
}
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h (revision 201559)
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h (working copy)
@@ -28,7 +28,8 @@
class Target;
class raw_ostream;
-extern Target TheAArch64Target;
+extern Target TheAArch64leTarget;
+extern Target TheAArch64beTarget;
namespace AArch64_MC {
MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU,
@@ -41,12 +42,17 @@
MCContext &Ctx);
MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS,
- uint8_t OSABI);
+ uint8_t OSABI,
+ bool IsLittleEndian);
-MCAsmBackend *createAArch64AsmBackend(const Target &T,
+MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU);
+MCAsmBackend *createAArch64beAsmBackend(const Target &T,
+ const MCRegisterInfo &MRI,
+ StringRef TT, StringRef CPU);
+
} // End llvm namespace
// Defines symbolic names for AArch64 registers. This defines a mapping from
Index: lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
===================================================================
--- lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp (revision 201559)
+++ lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp (working copy)
@@ -16,9 +16,12 @@
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-Target llvm::TheAArch64Target;
+Target llvm::TheAArch64leTarget;
+Target llvm::TheAArch64beTarget;
extern "C" void LLVMInitializeAArch64TargetInfo() {
RegisterTarget<Triple::aarch64, /*HasJIT=*/true>
- X(TheAArch64Target, "aarch64", "AArch64 (ARM 64-bit target)");
+ X(TheAArch64leTarget, "aarch64", "AArch64 (ARM 64-bit little endian target)");
+ RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true>
+ Y(TheAArch64beTarget, "aarch64_be", "AArch64 (ARM 64-bit big endian target)");
}
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