[llvm] r200957 - X86: Resolve a long standing FIXME and properly isel pextr[bw].
Jim Grosbach
grosbach at apple.com
Thu Feb 6 16:16:34 PST 2014
Author: grosbach
Date: Thu Feb 6 18:16:33 2014
New Revision: 200957
URL: http://llvm.org/viewvc/llvm-project?rev=200957&view=rev
Log:
X86: Resolve a long standing FIXME and properly isel pextr[bw].
Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use
them to match the relevant pextr store instructions.
The test widen_load-2.ll requires a slight change because with the
stores gone, the remaining instructions are scheduled in a different
order.
Add test cases for SSE4 and AVX variants.
Resolves rdar://13414672.
Patch by Adam Nemet <anemet at apple.com>.
Added:
llvm/trunk/test/CodeGen/X86/extract-store.ll
Modified:
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
llvm/trunk/lib/Target/X86/README-SSE.txt
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/widen_load-2.ll
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=200957&r1=200956&r2=200957&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Feb 6 18:16:33 2014
@@ -492,6 +492,12 @@ def intrinsic_wo_chain : SDNode<"ISD::IN
// Do not use cvt directly. Use cvt forms below
def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
+def SDT_assertext : SDTypeProfile<1, 1,
+ [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
+def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
+def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
+
+
//===----------------------------------------------------------------------===//
// Selection DAG Condition Codes
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td?rev=200957&r1=200956&r2=200957&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrNEON.td Thu Feb 6 18:16:33 2014
@@ -64,11 +64,6 @@ def Neon_vextract : SDNode<"AArch64ISD::
[SDTCisVec<0>, SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
-def SDT_assertext : SDTypeProfile<1, 1,
- [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
-def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
-def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
-
//===----------------------------------------------------------------------===//
// Addressing-mode instantiations
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/README-SSE.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=200957&r1=200956&r2=200957&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/README-SSE.txt (original)
+++ llvm/trunk/lib/Target/X86/README-SSE.txt Thu Feb 6 18:16:33 2014
@@ -494,11 +494,6 @@ is memory.
//===---------------------------------------------------------------------===//
-SSE4 extract-to-mem ops aren't being pattern matched because of the AssertZext
-sitting between the truncate and the extract.
-
-//===---------------------------------------------------------------------===//
-
INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
any number of 0.0 simultaneously. Currently we only use it for simple
insertions.
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=200957&r1=200956&r2=200957&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Feb 6 18:16:33 2014
@@ -6210,10 +6210,8 @@ multiclass SS41I_extract8<bits<8> opc, s
(ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
-// FIXME:
-// There's an AssertZext in the way of writing the store pattern
-// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+ [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
+ imm:$src2)))), addr:$dst)]>;
}
let Predicates = [HasAVX] in
@@ -6236,10 +6234,8 @@ multiclass SS41I_extract16<bits<8> opc,
(ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
-// FIXME:
-// There's an AssertZext in the way of writing the store pattern
-// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+ [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
+ imm:$src2)))), addr:$dst)]>;
}
let Predicates = [HasAVX] in
Added: llvm/trunk/test/CodeGen/X86/extract-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extract-store.ll?rev=200957&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/extract-store.ll (added)
+++ llvm/trunk/test/CodeGen/X86/extract-store.ll Thu Feb 6 18:16:33 2014
@@ -0,0 +1,22 @@
+; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.1 | FileCheck %s -check-prefix=SSE41
+; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+avx | FileCheck %s -check-prefix=AVX
+
+define void @pextrb(i8* nocapture %dst, <16 x i8> %foo) {
+; AVX: vpextrb
+; SSE41: pextrb
+; AVX-NOT: movb
+; SSE41-NOT: movb
+ %vecext = extractelement <16 x i8> %foo, i32 15
+ store i8 %vecext, i8* %dst, align 1
+ ret void
+}
+
+define void @pextrw(i16* nocapture %dst, <8 x i16> %foo) {
+; AVX: vpextrw
+; SSE41: pextrw
+; AVX-NOT: movw
+; SSE41-NOT: movw
+ %vecext = extractelement <8 x i16> %foo, i32 15
+ store i16 %vecext, i16* %dst, align 1
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/X86/widen_load-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=200957&r1=200956&r2=200957&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_load-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_load-2.ll Thu Feb 6 18:16:33 2014
@@ -149,9 +149,9 @@ define void @add31i8(%i8vec31* nocapture
; CHECK: movdqa
; CHECK: paddb
; CHECK: paddb
-; CHECK: movq
; CHECK: pextrb
; CHECK: pextrw
+; CHECK: movq
; CHECK: ret
%a = load %i8vec31* %ap, align 16
%b = load %i8vec31* %bp, align 16
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