[PATCH] Forbid the use of registers t6, t7 and t8 if the target is MIPS NaCl.
Sasa Stankovic
Sasa.Stankovic at imgtec.com
Wed Feb 5 10:58:26 PST 2014
The patch is updated
Hi mseaborn,
http://llvm-reviews.chandlerc.com/D2694
CHANGE SINCE LAST DIFF
http://llvm-reviews.chandlerc.com/D2694?vs=6862&id=6902#toc
Files:
lib/Target/Mips/MipsCallingConv.td
lib/Target/Mips/MipsRegisterInfo.cpp
lib/Target/Mips/MipsSubtarget.h
test/CodeGen/Mips/fastcc.ll
test/CodeGen/Mips/nacl-reserved-regs.ll
Index: lib/Target/Mips/MipsCallingConv.td
===================================================================
--- lib/Target/Mips/MipsCallingConv.td
+++ lib/Target/Mips/MipsCallingConv.td
@@ -192,8 +192,13 @@
// Integer arguments are passed in integer registers. All scratch registers,
// except for AT, V0 and T9, are available to be used as argument registers.
- CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6,
- T7, T8, V1]>>,
+ CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()",
+ CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
+
+ // In NaCl, T6, T7 and T8 are reserved and not available as argument
+ // registers for fastcc.
+ CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
+ CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
// f32 arguments are passed in single-precision floating pointer registers.
CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
Index: lib/Target/Mips/MipsRegisterInfo.cpp
===================================================================
--- lib/Target/Mips/MipsRegisterInfo.cpp
+++ lib/Target/Mips/MipsRegisterInfo.cpp
@@ -134,6 +134,17 @@
for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
Reserved.set(ReservedGPR32[I]);
+ // Reserved for NaCl use. T6 contains the mask for sandboxing control flow
+ // (indirect jumps and calls). T7 contains the mask for sandboxing memory
+ // accesses (loads and stores). T8 contains the thread pointer.
+ if (Subtarget.isTargetNaCl()) {
+ static const uint16_t PnaclReservedCPURegs[] = {
+ Mips::T6, Mips::T7, Mips::T8
+ };
+ for (unsigned I = 0; I < array_lengthof(PnaclReservedCPURegs); ++I)
+ Reserved.set(PnaclReservedCPURegs[I]);
+ }
+
for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
Reserved.set(ReservedGPR64[I]);
Index: lib/Target/Mips/MipsSubtarget.h
===================================================================
--- lib/Target/Mips/MipsSubtarget.h
+++ lib/Target/Mips/MipsSubtarget.h
@@ -209,6 +209,7 @@
bool os16() const { return Os16;};
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
+ bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
// for now constant islands are on for the whole compilation unit but we only
// really use them if in addition we are in mips16 mode
Index: test/CodeGen/Mips/fastcc.ll
===================================================================
--- test/CodeGen/Mips/fastcc.ll
+++ test/CodeGen/Mips/fastcc.ll
@@ -1,4 +1,7 @@
; RUN: llc < %s -march=mipsel | FileCheck %s
+; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu \
+; RUN: | FileCheck %s -check-prefix=CHECK-NACL
+
@gi0 = external global i32
@gi1 = external global i32
@@ -95,6 +98,11 @@
; CHECK: lw $5
; CHECK: lw $4
+; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
+; CHECK-NACL-NOT: lw $14
+; CHECK-NACL-NOT: lw $15
+; CHECK-NACL-NOT: lw $24
+
%0 = load i32* @gi0, align 4
%1 = load i32* @gi1, align 4
%2 = load i32* @gi2, align 4
@@ -134,6 +142,11 @@
; CHECK: sw $24
; CHECK: sw $3
+; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
+; CHECK-NACL-NOT: sw $14
+; CHECK-NACL-NOT: sw $15
+; CHECK-NACL-NOT: sw $24
+
store i32 %a0, i32* @g0, align 4
store i32 %a1, i32* @g1, align 4
store i32 %a2, i32* @g2, align 4
Index: test/CodeGen/Mips/nacl-reserved-regs.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/nacl-reserved-regs.ll
@@ -0,0 +1,86 @@
+; RUN: llc -march=mipsel -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
+; RUN: | FileCheck %s -check-prefix=CHECK-NACL
+
+ at g0 = external global i32
+ at g1 = external global i32
+ at g2 = external global i32
+ at g3 = external global i32
+ at g4 = external global i32
+ at g5 = external global i32
+ at g6 = external global i32
+ at g7 = external global i32
+ at g8 = external global i32
+ at g9 = external global i32
+ at g10 = external global i32
+ at g11 = external global i32
+ at g12 = external global i32
+ at g13 = external global i32
+ at g14 = external global i32
+ at g15 = external global i32
+ at g16 = external global i32
+ at g17 = external global i32
+ at g18 = external global i32
+ at g19 = external global i32
+ at g20 = external global i32
+ at g21 = external global i32
+ at g22 = external global i32
+ at g23 = external global i32
+ at g24 = external global i32
+ at g25 = external global i32
+ at g26 = external global i32
+ at g27 = external global i32
+
+declare void @f2(i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32)
+
+define void @f() {
+entry:
+ ; Mips can hold at most 28 integer values in registers at the same time (all
+ ; registers except $zero, k0, k1 and sp can be used).
+ %0 = load i32* @g0
+ %1 = load i32* @g1
+ %2 = load i32* @g2
+ %3 = load i32* @g3
+ %4 = load i32* @g4
+ %5 = load i32* @g5
+ %6 = load i32* @g6
+ %7 = load i32* @g7
+ %8 = load i32* @g8
+ %9 = load i32* @g9
+ %10 = load i32* @g10
+ %11 = load i32* @g11
+ %12 = load i32* @g12
+ %13 = load i32* @g13
+ %14 = load i32* @g14
+ %15 = load i32* @g15
+ %16 = load i32* @g16
+ %17 = load i32* @g17
+ %18 = load i32* @g18
+ %19 = load i32* @g19
+ %20 = load i32* @g20
+ %21 = load i32* @g21
+ %22 = load i32* @g22
+ %23 = load i32* @g23
+ %24 = load i32* @g24
+ %25 = load i32* @g25
+ %26 = load i32* @g26
+ %27 = load i32* @g27
+ call void @f2(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7,
+ i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14,
+ i32 %15, i32 %16, i32 %17, i32 %18, i32 %19, i32 %20, i32 %21,
+ i32 %22, i32 %23, i32 %24, i32 %25, i32 %26, i32 %27)
+ ret void
+
+; Check that t6, t7 and t8 are used in non-NaCl code.
+; CHECK: lw $14
+; CHECK: lw $15
+; CHECK: lw $24
+
+; t6, t7 and t8 are reserved in NaCl.
+; CHECK-NACL-NOT: lw $14
+; CHECK-NACL-NOT: lw $15
+; CHECK-NACL-NOT: lw $24
+}
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