[PATCH] Add NaCl target for Mips. Forbid indexed loads and stores if the target is NaCl.

[Sasa Stankovic]

================
Comment at: lib/Target/Mips/MipsInstrFPU.td:393
@@ -392,3 +392,3 @@
 // Indexed loads and stores.
-let Predicates = [HasFPIdx, HasStdEnc] in {
+let Predicates = [HasFPIdx, HasStdEnc, IsNotNaCl] in {
   def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
----------------
Mark Seaborn wrote:
> Petar Jovanovic wrote:
> > Mark Seaborn wrote:
> > > It might be worth commenting why these instructions are disallowed under NaCl -- either in the code or at least in the commit message -- because I don't actually know why they are.
> > > 
> > > Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet?
> > > Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet?
> > 
> > Similar to ARM, register-indexed addressing is not supported by design in MIPS NaCl.
> OK, I see.  Is it the "x" in the instruction name that indicates this addressing mode?  Which part of the tablegen definition indicates this addressing mode?
> 
> Maybe comment something like:
> '"x" indicates a base register + offset register addressing mode which is disallowed under NaCl'
> 
> Which part of the tablegen definition indicates this addressing mode?

All indexed loads and stores derive from tablegen classes LWXC1_FT and SWXC1_FT where base and offset are defined to have type PtrRC (or ptr_rc), which represents, if I understand correctly, a pointer value operand whose register class is resolved by using the TargetRegisterInfo::getPointerRegClass() hook at codegen time.


http://llvm-reviews.chandlerc.com/D2690