[PATCH 1/1] R600: Enable vector fpow.

[Tom Stellard]

On Fri, Jan 31, 2014 at 08:01:52PM -0500, Jan Vesely wrote:
> The OpenCL specs say: "The vector versions of the math functions operate
> component-wise. The description is per-component."
> 
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> CC: Tom Stellard <thomas.stellard at amd.com>
> ---
> Hi,
> 
> this patch enables vector pow. The OpenCL specs say that vector op is
> per-component. LLVM pow intrinsic allows vectors too, but does not specify
> behavior in vector case, so I assumed it was the same.
> 
> This patch fixes GEGL's "kernel_exposure" (operations/common/exposure.c).
> 
> I'm not sure about the test part, as I don't know what influences the order of
> operations.
> 

The test looks good to me, but you should use CHECK-LABEL when checking the function
name instead of CHECK:  I can fix this up before I commit it.  Thanks for the patch!

-Tom

> regards,
> Jan
> 
>  lib/Target/R600/AMDGPUISelLowering.cpp |  1 +
>  test/CodeGen/R600/llvm.pow.ll          | 29 +++++++++++++++++++++++++----
>  2 files changed, 26 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
> index e0ed721..f97a53f 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.cpp
> +++ b/lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -185,6 +185,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
>      setOperationAction(ISD::FABS, VT, Expand);
>      setOperationAction(ISD::FADD, VT, Expand);
>      setOperationAction(ISD::FDIV, VT, Expand);
> +    setOperationAction(ISD::FPOW, VT, Expand);
>      setOperationAction(ISD::FFLOOR, VT, Expand);
>      setOperationAction(ISD::FTRUNC, VT, Expand);
>      setOperationAction(ISD::FMUL, VT, Expand);
> diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll
> index b587d2b..af84a1a 100644
> --- a/test/CodeGen/R600/llvm.pow.ll
> +++ b/test/CodeGen/R600/llvm.pow.ll
> @@ -1,10 +1,11 @@
>  ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>  
> -;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
> -;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
> +;CHECK: test1:
> +;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
>  
> -define void @test(<4 x float> inreg %reg0) #0 {
> +define void @test1(<4 x float> inreg %reg0) #0 {
>     %r0 = extractelement <4 x float> %reg0, i32 0
>     %r1 = extractelement <4 x float> %reg0, i32 1
>     %r2 = call float @llvm.pow.f32( float %r0, float %r1)
> @@ -13,7 +14,27 @@ define void @test(<4 x float> inreg %reg0) #0 {
>     ret void
>  }
>  
> +;CHECK: test2:
> +;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
> +;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
> +;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
> +;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
> +define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
> +   %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
> +   call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
> +   ret void
> +}
> +
>  declare float @llvm.pow.f32(float ,float ) readonly
> +declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly
>  declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>  
>  attributes #0 = { "ShaderType"="0" }
> -- 
> 1.8.5.3
> 
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