[PATCH] [AArch64 NEON] Lower SELECT_CC with vector operand.

[Tim Northover]

  Hi Kevin,

  Some of that logic looks a little complicated. I can't see anything actually wrong with it, but it's rather difficult to check properly.

  That said, I only saw one hopefully unneeded part:


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:3026-3027
@@ +3025,4 @@
+      if (ResCC.getValueSizeInBits() > IfTrueVT.getSizeInBits()) {
+        unsigned eltnum =
+            EltNum * IfTrueVT.getSizeInBits() / ResCC.getValueSizeInBits();
+        EVT ExVT = EVT::getVectorVT(*DAG.getContext(), CEltT, eltnum);
----------------
Two variables differing in just case is not a good idea.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:3012-3025
@@ +3011,16 @@
+                                  IfTrueVT.getVectorNumElements());
+    if (CEltT.getSizeInBits() < IfTrueVT.getSizeInBits()) {
+      EVT DUPVT =
+          EVT::getVectorVT(*DAG.getContext(), CEltT,
+                           IfTrueVT.getSizeInBits() / CEltT.getSizeInBits());
+      ResCC = DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, DUPVT, ResCC,
+                          DAG.getConstant(0, MVT::i64, false));
+
+      ResCC = DAG.getNode(ISD::BITCAST, dl, CastVT, ResCC);
+    } else {
+      // FIXME: If IfTrue & IfFalse hold v1i8, v1i16 or v1i32, this function
+      // can't handle them and will hit this assert.
+      assert(CEltT.getSizeInBits() == IfTrueVT.getSizeInBits() &&
+             "Vector of IfTrue & IfFalse is too small.");
+      if (ResCC.getValueSizeInBits() > IfTrueVT.getSizeInBits()) {
+        unsigned eltnum =
----------------
This 3-way logic is a bit difficult to follow. It looks like it should be expressible as "if (compare result < iftrue) DUP else if (compare result > iftrue) EXTRACT_SUBVEC" but it switches from CEltT to ResCC half-way through. Is that really necessary?


http://llvm-reviews.chandlerc.com/D2639