[llvm] r200130 - Fix swapped CASA operands.

[Jakob Stoklund Olesen]

Author: stoklund
Date: Sun Jan 26 00:09:54 2014
New Revision: 200130

URL: http://llvm.org/viewvc/llvm-project?rev=200130&view=rev
Log:
Fix swapped CASA operands.

Found by SingleSource/UnitTests/AtomicOps.c

Modified:
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/test/CodeGen/SPARC/atomics.ll

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=200130&r1=200129&r2=200130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sun Jan 26 00:09:54 2014
@@ -2977,7 +2977,7 @@ SparcTargetLowering::expandAtomicRMW(Mac
   // loop:
   //   %val = phi %val0, %dest
   //   %upd = op %val, %rs2
-  //   %dest = cas %addr, %upd, %val
+  //   %dest = cas %addr, %val, %upd
   //   cmp %val, %dest
   //   bne loop
   // done:
@@ -3036,7 +3036,7 @@ SparcTargetLowering::expandAtomicRMW(Mac
   }
 
   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
-    .addReg(AddrReg).addReg(UpdReg).addReg(ValReg)
+    .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
     .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
   BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))

Modified: llvm/trunk/test/CodeGen/SPARC/atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/atomics.ll?rev=200130&r1=200129&r2=200130&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/atomics.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/atomics.ll Sun Jan 26 00:09:54 2014
@@ -64,8 +64,8 @@ entry:
 
 ; CHECK-LABEL: test_load_add_32
 ; CHECK: membar
-; CHECK: add
-; CHECK: cas [%o0]
+; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
+; CHECK: cas [%o0], [[V]], [[U]]
 ; CHECK: membar
 define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
 entry: