[PATCH] [AArch64 NEON] Fix pattern match failed on FP_ROUND from v1f128 to v1f64.

[Weiming Zhao]

Hi Kevin,

This patch looks good to me.
Actually, we're just going to submit a patch for fp_round, which is almost the same as yours. 

Thanks for the patch.
Weiming

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Kevin Qin
Sent: Friday, January 24, 2014 2:38 AM
To: kevinqindev at gmail.com; t.p.northover at gmail.com
Cc: llvm-commits at cs.uiuc.edu
Subject: [PATCH] [AArch64 NEON] Fix pattern match failed on FP_ROUND from v1f128 to v1f64.

Hi,

Please review, thanks.

http://llvm-reviews.chandlerc.com/D2613

Files:
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  test/CodeGen/AArch64/neon-fpround_f128.ll

Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -541,6 +541,7 @@
   SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
   SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
   SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
+  SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
 
   //===--------------------------------------------------------------------===//
   // Vector Splitting Support: LegalizeVectorTypes.cpp
Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -384,6 +384,9 @@
     case ISD::STORE:
       Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
       break;
+    case ISD::FP_ROUND:
+      Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
+      break;
     }
   }
 
@@ -467,6 +470,15 @@
                       N->getOriginalAlignment(), N->getTBAAInfo());  }
 
+/// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that 
+needs /// to be scalarized, it must be <1 x ty>.  Convert the element instead.
+SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned 
+OpNo) {
+  SDValue Elt = GetScalarizedVector(N->getOperand(0));
+  SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
+                            N->getValueType(0).getVectorElementType(), Elt,
+                            N->getOperand(1));
+  return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), 
+N->getValueType(0), Res); }
 
 //===----------------------------------------------------------------------===//
 //  Result Vector Splitting
Index: test/CodeGen/AArch64/neon-fpround_f128.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/neon-fpround_f128.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu 
+-mattr=+neon -fp-contract=fast | FileCheck %s
+
+define <1 x double> @test_fpround_v1f128(<1 x fp128>* %a) { ; 
+CHECK-LABEL: test_fpround_v1f128:
+; CHECK: bl __trunctfdf2
+  %b = load <1 x fp128>* %a
+  %c = fptrunc <1 x fp128> %b to <1 x double>
+  ret <1 x double> %c
+}
+
+define <2 x double> @test_fpround_v2f128(<2 x fp128>* %a) { ; 
+CHECK-LABEL: test_fpround_v2f128:
+; CHECK: bl __trunctfdf2
+; CHECK: bl __trunctfdf2
+  %b = load <2 x fp128>* %a
+  %c = fptrunc <2 x fp128> %b to <2 x double>
+  ret <2 x double> %c
+}