[llvm] r199766 - Fix PR18572 - llc crash during GenericScheduler::initPolicy().

[Daniel Sanders]

Hi Andrew,

Did you mean to commit that testcase to test/CodeGen/Mips? It looks like it belongs in test/CodeGen/MSP430

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Andrew Trick
> Sent: 21 January 2014 21:28
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r199766 - Fix PR18572 - llc crash during
> GenericScheduler::initPolicy().
> 
> Author: atrick
> Date: Tue Jan 21 15:27:37 2014
> New Revision: 199766
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=199766&view=rev
> Log:
> Fix PR18572 - llc crash during GenericScheduler::initPolicy().
> 
> Generalized the heuristic that looks at the (very rough) size of the register
> file before enabling regpressure tracking.
> 
> Added:
>     llvm/trunk/test/CodeGen/Mips/misched-msp430.ll
> Modified:
>     llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=199766&r1=19
> 9765&r2=199766&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Jan 21 15:27:37
> 2014
> @@ -2531,10 +2531,16 @@ void GenericScheduler::initPolicy(Machin
>    // Avoid setting up the register pressure tracker for small regions to save
>    // compile time. As a rough heuristic, only track pressure when the number
> of
>    // schedulable instructions exceeds half the integer register file.
> -  unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
> -    TM.getTargetLowering()->getRegClassFor(MVT::i32));
> -
> -  RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
> +  RegionPolicy.ShouldTrackPressure = true;  unsigned LegalIntVT =
> + MVT::i32;  for (; LegalIntVT > (unsigned)MVT::i1; --LegalIntVT) {
> +    if (TM.getTargetLowering()-
> >isTypeLegal((MVT::SimpleValueType)LegalIntVT)) {
> +      unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
> +        TM.getTargetLowering()->getRegClassFor(
> +          (MVT::SimpleValueType)LegalIntVT));
> +      RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
> +    }
> +  }
> 
>    // For generic targets, we default to bottom-up, because it's simpler and
> more
>    // compile-time optimizations have been implemented in that direction.
> 
> Added: llvm/trunk/test/CodeGen/Mips/misched-msp430.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/misched-
> msp430.ll?rev=199766&view=auto
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/misched-msp430.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/misched-msp430.ll Tue Jan 21 15:27:37
> +++ 2014
> @@ -0,0 +1,20 @@
> +; RUN: llc < %s -mtriple=msp430-unknown-unknown -enable-misched |
> +FileCheck %s
> +
> +target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
> +
> + at y = common global i16 0, align 2
> + at x = common global i16 0, align 2
> +
> +; Test that the MI Scheduler's initPolicy does not crash when i32 is ;
> +unsupported. The content of the asm check below is unimportant. It ;
> +only verifies that the code generator ran succesfully.
> +;
> +; CHECK-LABEL: @f
> +; CHECK: mov.w &y, &x
> +; CHECK: ret
> +define void @f() {
> +entry:
> +  %0 = load i16* @y, align 2
> +  store i16 %0, i16* @x, align 2
> +  ret void
> +}
> 
> 
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