[llvm] r199809 - [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

[David Woodhouse]

Author: dwmw2
Date: Wed Jan 22 09:08:55 2014
New Revision: 199809

URL: http://llvm.org/viewvc/llvm-project?rev=199809&view=rev
Log:
[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/lib/Target/X86/X86InstrSystem.td
    llvm/trunk/test/MC/X86/index-operations.s
    llvm/trunk/test/MC/X86/x86-16.s
    llvm/trunk/test/MC/X86/x86-32.s
    llvm/trunk/test/MC/X86/x86-64.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Jan 22 09:08:55 2014
@@ -2332,16 +2332,17 @@ ParseInstruction(ParseInstructionInfo &I
       delete &Op;
     }
   }
-  // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
-  if (Name.startswith("ins") && Operands.size() == 3 &&
-      (Name == "insb" || Name == "insw" || Name == "insl")) {
-    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
-    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
-    if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
-      Operands.pop_back();
-      Operands.pop_back();
-      delete &Op;
-      delete &Op2;
+
+  // Append default arguments to "ins[bwld]"
+  if (Name.startswith("ins") && Operands.size() == 1 &&
+      (Name == "insb" || Name == "insw" || Name == "insl" ||
+       Name == "insd" )) {
+    if (isParsingIntelSyntax()) {
+      Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
+      Operands.push_back(DefaultMemDIOperand(NameLoc));
+    } else {
+      Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
+      Operands.push_back(DefaultMemDIOperand(NameLoc));
     }
   }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Wed Jan 22 09:08:55 2014
@@ -116,9 +116,12 @@ let Uses = [EAX] in
 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
                   "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
 
-def IN8  : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
-def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>,  OpSize;
-def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;
+def IN8  : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
+             "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
+def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
+             "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>,  OpSize;
+def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
+             "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/MC/X86/index-operations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/index-operations.s?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/index-operations.s (original)
+++ llvm/trunk/test/MC/X86/index-operations.s Wed Jan 22 09:08:55 2014
@@ -139,3 +139,8 @@ outsw %fs:(%esi), %dx
 // 64: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x67,0x6f]
 // 32: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x6f]
 // 16: outsw %fs:(%esi), %dx # encoding: [0x64,0x67,0x6f]
+
+insw %dx, (%edi)
+// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d]
+// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
+// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d]

Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Wed Jan 22 09:08:55 2014
@@ -809,17 +809,17 @@ pshufw $90, %mm4, %mm0
 	outsl	%ds:(%si), %dx
 	outsl	(%si), %dx
 
-// CHECK: insb # encoding: [0x6c]
+// CHECK: insb %dx, %es:(%di) # encoding: [0x6c]
 // CHECK: insb
 	insb
 	insb	%dx, %es:(%di)
 
-// CHECK: insw # encoding: [0x6d]
+// CHECK: insw %dx, %es:(%di) # encoding: [0x6d]
 // CHECK: insw
 	insw
 	insw	%dx, %es:(%di)
 
-// CHECK: insl # encoding: [0x66,0x6d]
+// CHECK: insl %dx, %es:(%di) # encoding: [0x66,0x6d]
 // CHECK: insl
 	insl
 	insl	%dx, %es:(%di)

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Wed Jan 22 09:08:55 2014
@@ -885,17 +885,17 @@ pshufw $90, %mm4, %mm0
 	outsl	%ds:(%esi), %dx
 	outsl	(%esi), %dx
 
-// CHECK: insb # encoding: [0x6c]
+// CHECK: insb %dx, %es:(%edi) # encoding: [0x6c]
 // CHECK: insb
 	insb
 	insb	%dx, %es:(%edi)
 
-// CHECK: insw # encoding: [0x66,0x6d]
+// CHECK: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
 // CHECK: insw
 	insw
 	insw	%dx, %es:(%edi)
 
-// CHECK: insl # encoding: [0x6d]
+// CHECK: insl %dx, %es:(%edi) # encoding: [0x6d]
 // CHECK: insl
 	insl
 	insl	%dx, %es:(%edi)

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=199809&r1=199808&r2=199809&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Wed Jan 22 09:08:55 2014
@@ -1070,17 +1070,17 @@ xsetbv // CHECK: xsetbv # encoding: [0x0
 	outsl	%ds:(%rsi), %dx
 	outsl	(%rsi), %dx
 
-// CHECK: insb # encoding: [0x6c]
+// CHECK: insb  %dx, %es:(%rdi) # encoding: [0x6c]
 // CHECK: insb
 	insb
 	insb	%dx, %es:(%rdi)
 
-// CHECK: insw # encoding: [0x66,0x6d]
+// CHECK: insw  %dx, %es:(%rdi) # encoding: [0x66,0x6d]
 // CHECK: insw
 	insw
 	insw	%dx, %es:(%rdi)
 
-// CHECK: insl # encoding: [0x6d]
+// CHECK: insl %dx, %es:(%rdi) # encoding: [0x6d]
 // CHECK: insl
 	insl
 	insl	%dx, %es:(%rdi)