[llvm] r199343 - Adjust offsets for max load instruction offsets. This is more pessimistic

Reed Kotler rkotler at mips.com
Wed Jan 15 16:47:46 PST 2014


Author: rkotler
Date: Wed Jan 15 18:47:46 2014
New Revision: 199343

URL: http://llvm.org/viewvc/llvm-project?rev=199343&view=rev
Log:
Adjust offsets for max load instruction offsets. This is more pessimistic
than it needs to be by 1 bit but I need to finish some other things so 
that all the boundary cases will work in that situation. constpool.c
in test-suite will fail to assemble under our new internal test-suite sync
without this change.


Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
    llvm/trunk/test/CodeGen/Mips/const6a.ll

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=199343&r1=199342&r2=199343&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Wed Jan 15 18:47:46 2014
@@ -119,6 +119,7 @@ class FJAL16_ins<bits<1> _X, string asms
          !strconcat(asmstr, "\t$imm\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
+  let Size=6;
 }
 
 class FJALB16_ins<bits<1> _X, string asmstr,
@@ -127,6 +128,7 @@ class FJALB16_ins<bits<1> _X, string asm
          !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
+  let Size=6;
 }
 
 //

Modified: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=199343&r1=199342&r2=199343&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp Wed Jan 15 18:47:46 2014
@@ -790,11 +790,11 @@ initializeFunctionInfo(const std::vector
             Bits = 8;
             Scale = 4;
             LongFormOpcode = Mips::LwRxPcTcpX16;
-            LongFormBits = 16;
+            LongFormBits = 14;
             LongFormScale = 1;
             break;
           case Mips::LwRxPcTcpX16:
-            Bits = 16;
+            Bits = 14;
             Scale = 1;
             NegOk = true;
             break;

Modified: llvm/trunk/test/CodeGen/Mips/const6a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/const6a.ll?rev=199343&r1=199342&r2=199343&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/const6a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/const6a.ll Wed Jan 15 18:47:46 2014
@@ -19,7 +19,7 @@ entry:
 ; load-relax: $CPI0_0:
 ; load-relax:	.4byte	3735943886
 ; load-relax:	.end	t
-  call void asm sideeffect ".space 40000", ""() #1, !srcloc !1
+  call void asm sideeffect ".space 10000", ""() #1, !srcloc !1
   ret void
 }
 





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